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MCM6729 Datasheet(PDF) 3 Page - Motorola, Inc

Part No. MCM6729
Description  256K x 4 Bit Fast Static Random Access Memory
Download  8 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MCM6729 Datasheet(HTML) 3 Page - Motorola, Inc

   
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MCM6729
3
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Typ
Max
Unit
Address Input Capacitance
Cin
6
pF
Control Pin Input Capacitance
Cin
6
pF
Input/Output Capacitance
CI/O
8
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ±10%, TA = 0 to +70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . . . .
Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
2 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . .
Output Load
See Figure 1A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE TIMING (See Notes 1 and 2)
MCM6729–10
MCM6729–12
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
10
12
ns
3
Address Access Time
tAVQV
10
12
ns
Enable Access Time
tELQV
10
12
ns
Output Enable Access Time
tGLQV
5
6
ns
Output Hold from Address Change
tAXQX
3
3
ns
Enable Low to Output Active
tELQX
3
3
ns
4,5,6
Output Enable Low to Output Active
tGLQX
0
0
ns
4,5,6
Enable High to Output High–Z
tEHQZ
0
5
0
6
ns
4,5,6
Output Enable High to Output High–Z
tGHQZ
0
5
0
6
ns
4,5,6
NOTES:
1. W is high for read cycle.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHQZ (max) < tELQX (min), and tGHQZ (max) < tGLQX (min), both for a given device and from
device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VIL).
8. Addresses valid prior to or coincident with E going low.
AC TEST LOADS
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
VL = 1.5 V
Figure 1A
Figure 1B
5 p
+5 V
OUTPUT
255
480
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
TIMING LIMITS


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