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PSB7280 Datasheet(PDF) 94 Page - Siemens Semiconductor Group |
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PSB7280 Datasheet(HTML) 94 Page - Siemens Semiconductor Group |
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94 / 190 page  PSB 7280 Semiconductor Group 94 Data Sheet 1998-07-01 General Configuration Register Read/Write Address 2002 H Value after reset: B0 H PU Power Up 0 The DSP clock is turned off. It can be started again with a DSP interrupt. 1 Normal operation This is the value of PU after a hardware reset. CRS Clock Rate Select 0 Input DCL is twice the bit rate on IOM-2. 1 Input DCL is equal to the bit rate on IOM-2. CKOEN CLKO Enable 0 CLKO disabled (output high-impedance), CLKO generator initialized and idle. 1 Enables generation of CLKO (value during and after reset). When PU is ’0’ and CKOEN is ’0’, all outputs and input/outputs of the PSB 7280 are in the high-impedance state. CKOS Source clock for CLKO output pin 0 Internal DSP system clock is input for divider connected to CLKO. 1 CLKO outputs 7.68 MHz, may be used to clock e.g. an ISAC-S (value during and after reset). ODS Open drain select for IOM DU and DD lines: 0 DD and DU are open drain (reset value). 1 DD and DU are push-pull. CKOBR (18-16) Most significant bits of baud rate division factor for CLKO output from DSP clock. |
Similar Part No. - PSB7280 |
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Similar Description - PSB7280 |
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