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PSB7280 Datasheet(PDF) 88 Page - Siemens Semiconductor Group |
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PSB7280 Datasheet(HTML) 88 Page - Siemens Semiconductor Group |
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88 / 190 page  PSB 7280 Semiconductor Group 88 Data Sheet 1998-07-01 Interrupt Status Mask Register A ‘0’ in a bit position masks the corresponding interrupt (default value, i.e. after reset). The mask bit affects only the generation of the interrupt, but not the interrupt status bit from being set. Undocumented mask bits must be always set to ‘0’. Acknowledge Register The interrupt status bit is reset when the host writes a ‘1’ in the corresponding bit position. The other interrupts are acknowledged as follows: Note: Since no direct access to the MONR, CIR1, CIR2 and GP Int Status registers for the host is allowed (these registers are in the configuration and control register area 2000 H upwards), they are read using the procedure via address and data registers as decribed in Chapter 2 – in principle giving the host the possibility to handle the Monitor and C/I channels via the DSP. Bit 15 Bit 8 75 H T1 T2 T3 SAIN DINT HDLC1 HDCL2 Bit 7 Bit 0 74 H MDR MER MDA MEA MAB GPI CIC1 CIC2 Bit 15 Bit 8 77 H T1 T2 T3 SAIN Bit 7 Bit 0 76 H MER MDA MEA MAB DINT Reset when IND Int. Status register is read HDLC1 Reset when HDLC Controller 1 interrupt register is read HDLC2 Reset when HDLC Controller 2 interrupt register is read MDR Reset when MONR register is read GPI Reset when GP Int Status register is read CIC1 Reset when CIR1 register is read CIC2 Reset when CIR2 register is read. |
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