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PSB7280 Datasheet(PDF) 51 Page - Siemens Semiconductor Group |
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PSB7280 Datasheet(HTML) 51 Page - Siemens Semiconductor Group |
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51 / 190 page  PSB 7280 Semiconductor Group 51 Data Sheet 1998-07-01 Figure 19 Timing Generation on SAI Lines - Frame Sync For the frame sync signal RFS and/or TFS, two basic modes of operation are provided: Case 1 If control bit RCONT = 1, pulses on RFS are continuously and periodically generated if ERFS (Enable RFS generation control bit in HDLC register bank) is set to ‘1’, of one bit period length and spaced (PRD + 1) × 16 bits apart, where PRD = 0, 1, …, 31. Note: It suffices that the ERFS bits in one of the HDLC controller register banks is set to “1” in order for pulses to be generated. Case 2 If RCONT = 0, a burst of REP + 1 pulses on RFS is generated, of one bit period duration and spaced 16 bit periods apart when a start command is issued by setting the STR bit to ‘1’. REP takes a value in the range 0 to 1.023. Note: It suffices that the STR command in one of the HDLC controller register banks is issued in order for the generation of pulses start. The same applies for TFS (control bits are ETFS and STX). SCLK (in) DSP clock Div PRSC 10 M U X SCKIN 0 1 Baud-Rate Generator STR/ERFS 1 RCONT RPRD/RREP 1 10 RFS(in) 0 1 M U X RFIN RFS (out) 0 Baud-Rate Generator STX/ETFS 1 TCONT TPRD/TREP 1 10 TFS(in) 1 M U X TFIN TFS (out) SCLK (out) |
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