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PSB7238 Datasheet(PDF) 98 Page - Siemens Semiconductor Group |
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PSB7238 Datasheet(HTML) 98 Page - Siemens Semiconductor Group |
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98 / 190 page  PSB 7238 Register Description Semiconductor Group 98 Data Sheet 1998-07-01 Receive Audio Channel 2 Read/Write Address 2014 H - 2016H Value after reset: 00 H Note: Since the number of bits is 32 maximum, the value of the product (LBIT + 1) × (LEN + 1) shall not exceed 32. EN Enable If inactive (0), no clock is generated for this channel, must be set to 0 during configuration of receive audio channel 2. SLIN(1-0) Select Line 00 Channel time-slot on DU (frame sync FSC, clock DCL or DCL/2) 01 Channel time-slot on DD (frame sync FSC, clock DCL or DCL/2) 10 Channel time-slot on SR (frame sync RFS, clock SCLK) 11 Channel time-slot on ST (frame sync TFS, clock SCLK) LEN(4-0) Length of channel time-slot channel time-slot length in bits = LEN + 1 (1, …, 32 bits). TS(8-0) Time-slot position Position of first bit of time-slot from frame sync (0, …, 511). LMOD Load Mode 0 Sample of length LEN + 1 loaded into read register (from frame-1) at the occurrence of frame sync. 1(LBIT + 1) × (LEN + 1) bits are loaded into read register when ready (for software to be accessed via a ”Buffer Full” interrupt status). LBIT(4-0) Load Bits Number of bits in aggregates of (LEN + 1) loaded into read register when ready, if LMOD = 1. The number of bits loaded is equal to (LBIT + 1) × (LEN + 1), the corresponding interrupt status is BFUL2. |
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