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PSB7230 Datasheet(PDF) 77 Page - Siemens Semiconductor Group |
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PSB7230 Datasheet(HTML) 77 Page - Siemens Semiconductor Group |
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77 / 179 page  PSB 7230 Functional Blocks Semiconductor Group 77 Data Sheet 1998-07-01 4.5 Programming Indirectly Accessible Registers Registers in the memory mapped (DSP X-data RAM) area from 2000 H upwards are read and written: – via the Parallel Host Interface by using two registers (Conf/Cont Reg Address Register at address 40 H/3040H and Conf/Control Reg Data Register at address 41H/3041H) 4.5.1 Programming via Parallel Host Interface (see also Section 3.3.2) For writing a Configuration/Control register (addresses 2000 H - 203FH), the host writes in the Data register the data byte to be written and in the Address register the write command: where A(5:0) gives the offset of the register to be written. This causes an RACC (Register Access) interrupt status to the DSP. The DSP software transfers the Data byte to the requested address 2000 H + A(5:0) and writes the RDY bit (least significant bit of address 40 H/3040H) to “1” again (which was set to “0” by hardware at the time of writing of the Address register). By sensing the state of bit RDY the host is able to start a new access to Address and Data registers when the DSP is ready. For reading a Configuration/Control register (addresses 2000 H - 203FH), the host writes in the Address register the read command: where A(5:0) gives the offset of the register to be read. This causes a RACC (Register Access) interrupt status to the DSP. The DSP software transfers the contents of the requested address 2000 H + A(5:0) into the Data register and writes the RDY bit to “1”. Bit 7 Bit 0 0 0 A5 A4 A3 A2 A1 A0 Bit 7 Bit 0 1 0 A5 A4 A3 A2 A1 A0 |
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