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PSB7230 Datasheet(PDF) 42 Page - Siemens Semiconductor Group |
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PSB7230 Datasheet(HTML) 42 Page - Siemens Semiconductor Group |
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42 / 179 page  PSB 7230 Interfaces and Memory Organization Semiconductor Group 42 Data Sheet 1998-07-01 Software Interrupts For communication between the host software and the DSP software, the soft interrupt registers IND (from DSP to Host) and INH (from Host to DSP) can be used. Interrupt from Host to DSP A write operation by the Host to address 50 H (INH) causes a maskable INH interrupt status to be generated on INT1 to the DSP, and the Interrupt Host Busy bit INHB (address 50 H, readable by host) to be set to “1”. Having recognized an INH interrupt status, the DSP (firmware) reads address 3050 H (INH). This read operation automatically resets the HINT interrupt status bit in the DSP Interrupt Status Register for INT1 (address 3074 H). The INHB bit can be written by the DSP again to “0” to indicate that it is ready to accept a new interrupt from the host, which it would usually (but not necessarily) do after it has read the INH register. The 16-bit Control register located at 60/61 H (3060/3061H) may contain additional information for the DSP to read after an INH interrupt. Please refer to the specific interface procedures for details. Interrupt from DSP to Host For a soft interrupt from the DSP to the host, the procedure is identical. In this case, the soft interrupt is a maskable interrupt on line INT. The interrupt vector is written by the DSP in address 3058 H (IND). Simultaneously, the Interrupt DSP Busy bit INDB (address 58 H, writable by host) is set to “1”. Having recognized an IND interrupt status, the host reads address 58 H (IND), which automatically resets the DINT interrupt status bit in the Host Interrupt Status Register for INT (address 75 H). The INDB bit can be written by the host again to “0” to indicate that it is ready to accept a new interrupt from the DSP. The 16-bit Control register located at 60/61 H (3060/3061H) may contain additional information for the host to read after an IND interrupt. Please refer to the specific interface procedures for details. Registers for Accessing the External Memory In normal operation, the program bus of the DSP is connected via the external memory interface to the external memory bus so that instructions are fetched from an external memory when an address between 8000 H and FFFFH is hit, if EA = “High”. If EA = “Low”, the whole address range is for off-chip programs. If the bit LDMEM (see description of Configuration and Control Registers, Chapter 5.3) is set to ‘1’ and bit DACC is ‘0’ (see description of Configuration and Control Registers, Chapter 5.3), the external memory interface address and data buses are connected to the outputs of registers address low/high (at host address 44/45 H) and data low/high (at host address 46/47 H), respectively. This feature can be used to down-load programs into a memory connected to the PSB 7230. When a write access to the data high register (address 47 H) is detected, this activates the external memory interface write signal CWR for the duration of the host WR signal (independent of any possible wait states in NRW(3:0)). |
Similar Part No. - PSB7230 |
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Similar Description - PSB7230 |
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