MCM6726D

5

MOTOROLA FAST SRAM

6726D–8

6726D–10

6726D–12

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

8

—

10

—

12

—

ns

3

Address Setup Time

tAVWL

0

—

0

—

0

—

ns

Address Valid to End of Write

tAVWH

8

—

9

—

10

—

ns

Address Valid to End of Write, G High

tAVWH

7

—

8

—

9

—

ns

Write Pulse Width

tWLWH,

tWLEH

8

—

9

—

10

—

ns

Write Pulse Width, G High

tWLWH,

tWLEH

7

—

8

—

9

—

ns

Data Valid to End of Write

tDVWH

4

—

5

—

6

—

ns

Data Hold Time

tWHDX

0

—

0

—

0

—

ns

Write Low to Data High–Z

tWLQZ

—

4

—

5

—

6

ns

4,5,6

Write High to Output Active

tWHQX

3

—

3

—

3

—

ns

4,5,6

Write Recovery Time

tWHAX

0

—

0

—

0

—

ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.

3. All write cycle timings are referenced from the last valid address to the first transitioning address.

4. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.

5. This parameter is sampled and not 100% tested.

6. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.

WRITE CYCLE 1

DATA VALID

tDVWH

tAVWL

tAVWH

tAVAV

tWHAX

tWLWH

tWHDX

tWLQZ

tWHQX

HIGH–Z

HIGH–Z

A (ADDRESS)

W (WRITE ENABLE)

E (CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

tWLEH