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PEB2047 Datasheet(PDF) 23 Page - Siemens Semiconductor Group |
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PEB2047 Datasheet(HTML) 23 Page - Siemens Semiconductor Group |
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23 / 50 page  Semiconductor Group 23 PEB 2047 PEB 2047-16 4.2 Command Register (CMDR) Access in the multiplexed µP-interface mode: Write, address 2H Access in a demultiplexed µP-interface mode: Write, address 1H Address: 01H FSAD (2:0) Frame Synchronization signal Address 2 to 0; Address of the chosen FS signal 0 to 7 to be evaluated by the procedure started by SFE. SFE Start Frame Evaluation; a one in this bit position starts the frame evaluation procedure. A read operation on register FER will stop an unfinished frame evaluation procedure. RI Reset Incomplete instruction; if a three byte indirect register access is not completed the internal logic must be initialized again before a new three byte access is possible. STP0 … STP1 Start Procedure 1 and 0. The following procedures can be activated by these bits: Note: Before activating one of these procedures MOD:PSB has to be set to 0. During selftest or CM reset the device will ignore the external synchronization pulse and the user has no access to the internal data memory. Bit 7 Bit 0 0 FSAD2 FSAD1 FSAD0 SFE RI STP1 STP0 Table 4 STP Commands STP1 STP0 Function X 0 1 0 1 1 No operation Start control memory reset procedure Start selftest procedure |
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