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CDK3405ATQ48 Datasheet(PDF) 7 Page - Cadeka Microcircuits LLC. |
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CDK3405ATQ48 Datasheet(HTML) 7 Page - Cadeka Microcircuits LLC. |
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7 / 11 page  ©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 7 Data Sheet Functional Description WithintheCDK3405arethreeidentical8-bitD/A converters, each with a current source output. External loads are required to convert the current to voltage outputs. Data inputs RGB7-0 are overridden by the BLANK input. SYNC = H activates, sync current from IOS for sync-on-green video signals. Figure 2. CDK3405 Current Source Structure Digital Inputs Incoming GBR data is regsitered on the rising edge of the clock input, CLK. Analog outputs follow the rising edge of CLK after a delay, tDO. Clock Input - CLK Pixel data is registered on the rising edge of CLK. CLK should be driven by a dedicated buffer to avoid reflection induced jitter, overshoot, and undershoot. Pixel Data Inputs - R7-0, B7-0, G7-0 RGB digital inputs are registered on the rising edge of CLK. SYNC and BLANK SYNC and BLANK inputs control the output level (Figure 3 and Table 1, on the previous page) of the D/A convert- ers during CRT retrace intervals. BLANK forces the D/A outputs to the blanking level while SYNC = L turns off a current source, IOS, that is connected to the green D/A converter. SYNC = H adds a 112/256 fraction of full-scale current to the green output. SYNC = L extinguishes the sync current during the sync tip. BLANK gates the D/A inputs. If BLANK = HIGH, the D/A inputs control the output currents to be added to the out- put blanking level. If BLANK = Low, data inputs and the pedestal are disabled. Data: 660mV max. Pedestal: 54mV Sync: 286mV Figure 3. Normal Output Levels Sync Pulse Input - SYNC Bringing SYNC LOW, disables a current source which su- perimposes a sync pulse on the IOG output. SYNC and pixel data are registered on the rising edge of CLK. SYNC does not override any other data and should be used only during the blanking interval. If sync pulses are not re- quired, SYNC should be connected to GND. Blanking Input - BLANK When BLANK is LOW, pixel data inputs are ignored and the D/A converter outputs are driven to the blanking level. BLANK is registered on the rising edge of CLK. D/A Outputs Each D/A output is a current source from the VDDA supply. Expressed in current units, the GBR transformation from data to current is as follows: G = G7-0 & BLANK + SYNC * 112 B = B7-0 & BLANK R = R7-0 & BLANK Typical LSB current step is 73.2μA. To obtain a voltage output, a resistor must be connected to ground. Output voltage depends upon this external resistor, the reference voltage, and the value of the gain-setting resistor con- nected between RREF and GND. To implement a doubly-terminated 75Ω transmission line, a shunt 75Ω resistor should be placed adjacent to the analog output pin. With a terminated 75Ω line connected to the analog output, the load on the CDK3405 current source is 37.5Ω. VDDA SYNC VDDA VDDA G7-0 B7-0 VDDA R7-0 IOS VAA VAA VAA VAA |
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