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PA3332G-N24-T Datasheet(PDF) 7 Page - Unisonic Technologies |
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PA3332G-N24-T Datasheet(HTML) 7 Page - Unisonic Technologies |
7 / 10 page PA3332 Preliminary CMOS IC UNISONICTECHNOLOGIESCO.,LTD 7 of 10 www.unisonic.com.tw QW-R502-488.A Maximum Power Clampping Function The UTC PA3332 incorporated the maximum power clamping function that effectively reduces damage the speaker due to the larger power through the speaker. The Vol pin (pin 23) is weakly pull-low internally. If a non-zero voltage applies in the Vol pin, the UTC PA3332 will generate a high boundary voltage which the difference between the VDD/2 and the high boundary voltage is the same as the difference between the VDD/2 and the low boundary voltage. (i.e. VOH – VDD/2 = VDD/2 – VOL). Then the outputs of linear amplifiers will be effectively limited between the high/low boundary voltage, the maximum output power is clamped. Thus, the maximum power is controlled perfectively by means of setting the value of Vol, Note that if this function is not used, the Vol pin should be connected to the GND or be floated. Optimizing DEPOP Operation The UTC PA3332 contains a circuit that can reduce poping to minimum during the power-up or shutdown mode. The poping can be generated as long as a voltage step is applied to the speaker and the differential voltage generated at the two ends of the speaker. To get a minimum poping, the bypass capacitor is critical, 1/(CBx100kΩ) ≦ 1/(CI*(RI+RF)). (Where CB is the mid-rail bypass capacitor, 100kΩ is the output impedance of the mid-rail generator, RI is the input impedance, CI is the input coupling capacitor, RF is the gain setting impedance which is on the feedback path. CB is the most important capacitor. It can be applied in reducing the poping together with determining the rate at which the amplifier starts up during startup or recovery from shutdown mode.) The Figure B shows the de-poping circuit for the UTC PA3332. The PNP transistor effectively controls the voltage drop across the 50kΩ by slewing the internal node slowly when power is applied. At start-up, the voltage at BYPASS capacitor is zero. The PNP is ON to pull the mid-point of the bias circuit down. So the capacitor sees a lower effective voltage, and thus the charging is slower. This appears as a linear ramp (while the PNP transistor is conducting), followed by the expected exponential ramp of an RC circuit. 100kΩ 100kΩ 50kΩ Bypass VDD Figure B. |
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