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MCM63Z737 Datasheet(PDF) 12 Page - Motorola, Inc |
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MCM63Z737 Datasheet(HTML) 12 Page - Motorola, Inc |
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12 / 20 page  MCM63Z737 DMCM63Z819 12 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 5%, TA = 0 to 70°C Unless Otherwise Noted) Input Timing Measurement Reference Level 1.5 V . . . . . . . . . . . . . . . Input Pulse Levels 0 to 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Rise/Fall Time 1 V/ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . . . Output Timing Reference Level 1.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . Output Load See Figure 6 Unless Otherwise Noted . . . . . . . . . . . . . . R θJA Under Test TBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ/WRITE CYCLE TIMING (See Notes 1 and 2) P Sb l MCM63Z737–11 MCM63Z819–11 66 MHz MCM63Z737–15 MCM63Z819–15 50 MHz Ui N Parameter Symbol Min Max Min Max Unit Notes Cycle Time tKHKH 15 — 20 — ns Clock High Pulse Width tKHKL 6 — 8 — ns 3 Clock Low Pulse Width tKLKH 6 — 8 — ns 3 Clock Access Time tKHQV — 11 — 15 ns Output Enable to Output Valid tGLQV — 6 — 7 ns Clock High to Output Active tKHQX1 1.5 — 1.5 — ns 4, 5 Output Hold Time tKHQX 1.5 — 1.5 — ns 4 Output Enable to Output Active tGLQX 0 — 0 — ns 4, 5 Output Disable to Q High–Z tGHQZ — 4.5 — 5 ns 4, 5 Clock High to Q High–Z tKHQZ 1.5 4.5 1.5 5 ns 4, 5 Setup Times: Address ADV Data In Write Chip Enable Clock Enable tADKH tLVKH tDVKH tWVKH tEVKH tCVKH 2.5 2.5 2 2.5 2.5 2.5 — 2.5 2.5 2 2.5 2.5 2.5 — ns Hold Times: Address ADV Data In Write Chip Enable Clock Enable tKHAX tKHLX tKHDX tKHWX tKHEX tKHCX 0.5 0.5 0.5 0.5 0.5 0.5 — 0.5 0.5 0.5 0.5 0.5 0.5 — ns NOTES: 1. Write is defined as any SBx and SW low. Chip enable is defined as SE1 low, SE2 high, and SE3 low whenever ADV is low. 2. All read and write cycle timings are referenced from CK or G. 3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 4. This parameter is sampled and not 100% tested. 5. Measured at ± 200 mV from steady state. OUTPUT Z0 = 50 Ω RL = 50 Ω 1.5 V Figure 6. AC Test Load |
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