MCM6343

6

MOTOROLA FAST SRAM

P

Sb l

MCM6343–12

MCM6343–15

Ui

N

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

12

—

15

—

ns

4

Address Setup Time

tAVWL

0

—

0

—

ns

Address Valid to End of Write

tAVWH

10

—

12

—

ns

Address Valid to End of Write (G High)

tAVWH

9

—

10

—

ns

Write Pulse Width

tWLWH

tWLEH

10

—

12

—

ns

Write Pulse Width (G High)

tWLWH

tWLEH

9

—

10

—

ns

Data Valid to End of Write

tDVWH

6

—

7

—

ns

Data Hold Time

tWHDX

0

—

0

—

ns

Write Low to Data High–Z

tWLQZ

0

6

0

7

ns

5, 6, 7

Write High to Output Active

tWHQX

3

—

3

—

ns

5, 6, 7

Write Recovery Time

tWHAX

0

—

0

—

ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus

contention conditions during read and write cycles.

3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.

4. All write cycle timings are referenced from the last valid address to the first transitioning address.

5. This parameter is sampled and not 100% tested.

6. Transition is measured

± 200 mV from steady–state voltage.

7. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.

DATA VALID

tDVWH

tAVWL

tAVWH

tAVAV

tWHAX

tWLWH

tWHDX

tWLQZ

tWHQX

HIGH–Z

HIGH–Z

A (ADDRESS)

W (WRITE ENABLE)

E (CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

tWLEH

LB, UB (BYTE ENABLE)

WRITE CYCLE 1

(W Controlled; See Notes 1, 2, and 3)