MCM6343

4

MOTOROLA FAST SRAM

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 3.3 V ± 0.3 V, TA = 0 to + 70°C, Unless Otherwise Noted)

(TA = – 40 to + 85°C for Industrial Temperature Offering)

Logic Input Timing Measurement Reference Level

1.50 V

. . . . . . . .

Logic Input Pulse Levels

0 to 3.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time

2 ns

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level

1.50 V

. . . . . . . . . . . . . . . . . . . . . . . . .

Output Load

See Figure 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

P

Sb l

MCM6343–12

MCM6343–15

Ui

N

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

12

—

15

—

ns

4

Address Access Time

tAVQV

—

12

—

15

ns

Enable Access Time

tELQV

—

12

—

15

ns

5

Output Enable Access Time

tGLQV

—

6

—

7

ns

Output Hold from Address Change

tAXQX

3

—

3

—

ns

Enable Low to Output Active

tELQX

3

—

3

—

ns

6, 7, 8

Output Enable Low to Output Active

tGLQX

0

—

0

—

ns

6, 7, 8

Enable High to Output High–Z

tEHQZ

0

6

0

7

ns

6, 7, 8

Output Enable High to Output High–Z

tGHQZ

0

6

0

7

ns

6, 7, 8

Byte Enable Access Time

tBLQV

—

6

—

7

ns

Byte Enable Low to Output Active

tBLQX

0

—

0

—

ns

6, 7, 8

Byte High to Output High–Z

tBHQZ

0

6

0

7

ns

6, 7, 8

NOTES:

1. W is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus

contention conditions during read and write cycles.

3. Device is continuously selected (E

≤ VIL, G ≤ VIL).

4. All read cycle timings are referenced from the last valid address to the first transitioning address.

5. Addresses valid prior to or coincident with E going low.

6. At any given voltage and temperature, tEHQZ max t tELQX min, and tGHQZ max t tGLQX min, both for a given device and from device

to device.

7. This parameter is sampled and not 100% tested.

8. Transition is measured

± 200 mV from steady–state voltage.

The table of timing values shows either a minimum

or a maximum limit for each parameter. Input require-

ments are specified from the external system point of

view. Thus, address setup time is shown as a minimum

since the system must supply at least that much time.

On the other hand, responses from the memory are

specified from the device point of view. Thus, the ac-

cess time is shown as a maximum since the device

never provides data later than that time.

TIMING LIMITS

OUTPUT

Z0 = 50 Ω

RL = 50 Ω

VL = 1.5 V

Figure 1. AC Test Load