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MAX17048/MAX17049

Micropower 1-Cell/2-Cell Li+ ModelGauge ICs

characterization.

Note 2: All voltages are referenced to GND.

Note 3: Test is performed on unmounted/unsoldered parts.

Note 4: The voltage is trimmed and verified with 16x averaging.

Note 5: This current is always present.

to bridge the undefined region of the falling edge of SCL.

Note 11: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instance.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCL Clock Frequency

(Note 7)

0

400

kHz

Bus Free Time Between a

STOP and START Condition

1.3

F

s

START Condition (Repeated)

Hold Time

(Note 8)

0.6

F

s

Low Period of SCL Clock

1.3

F

s

High Period of SCL Clock

0.6

F

s

Setup Time for a Repeated

START Condition

0.6

F

s

Data Hold Time

(Notes 9, 10)

0

0.9

F

s

Data Setup Time

(Note 9)

100

ns

Rise Time of Both SDA and

SCL Signals

20 + 0.1CB

300

ns

Fall Time of Both SDA and SCL

Signals

20 + 0.1CB

300

ns

Setup Time for STOP Condition

0.6

F

s

Spike Pulse Widths

Suppressed by Input Filter

(Note 11)

0

50

ns

Capacitive Load for Each Bus

Line

(Note 12)

400

pF

SCL, SDA Input Capacitance

60

pF