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AK8859VQ Datasheet(PDF) 34 Page - Asahi Kasei Microsystems

Part # AK8859VQ
Description  NTSC/PAL/SECAM Digital Video Decoder
Download  73 Pages
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Manufacturer  AKM [Asahi Kasei Microsystems]
Direct Link  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AK8859VQ Datasheet(HTML) 34 Page - Asahi Kasei Microsystems

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[AK8859VQ]
MS1178-E-00
AKM Confidential
2010/04
- 34 -
[7.24] Clock generation
The AK8859VQ operates in the following three clock modes:
[7.24.1.] Line-locked clock mode
The “line-locked clock” is generated by PLL using horizontal sync signal within the input signal. If no input
signal is present, the AK8859VQ will switch from this mode to fixed-clock mode.
[7.24.2.] Frame-locked clock mode
The “frame-locked clock” is generated by PLL using vertical sync signal within the input signal. If no signal
is present, the AK8859VQ will switch from this mode to fixed-clock mode.
[7.24.3.] Fixed-clock mode
No PLL control is applied in this mode, which is enabled only when either it is set via the register or no input
signal is present. The sampling clock in this mode is 27MHz or 54MHz. In this mode, data capture cannot
be performed in EAV (end of active video), and must be performed in SAV (start of active video) format. The
number of pixels per line is not guarantee in this mode, but data guarantee is performed in the interval from
SAV to EAV.
[7.24.4.] Auto transition mode
The AK8859VQ transition function automatically switches among the above modes and selects the
optimum one, and when no input signal is present, it switches to the fixed-clock mode.
Setting for selection of clock generation mode
Sub Address: 0x08 [7:6]
Name
Setting value
Clock generation mode
Notes
[00]
Automatic
[01]
Line-locked
[10]
Frame-locked
CLKMODE0
~
CLKMODE1
[11]
Fixed-clock
[7.25.] PGA (Programmable Gain Amp)
The AK8859VQ digital PGA is built internally.
The digital PGA value can be set in range
−4.06dB~6.90dB.
Default gain setting is 0x3C(HEX)=0.00dB.
PGA gain equation:
Gain(dB)
(
)
+
×
=
5
.
401
5
.
251
5
.
2
20
PGA
LOG
*PGA:PGA1orPGA2 register value(Dec.)
At the default setting, when the composite video signal input with 0.5Vpp is input to the AIN pin, the decode
gain setting is set to appropriate range.


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