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AK8859VQ Datasheet(PDF) 18 Page - Asahi Kasei Microsystems |
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AK8859VQ Datasheet(HTML) 18 Page - Asahi Kasei Microsystems |
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18 / 73 page  [AK8859VQ] MS1178-E-00 AKM Confidential 2010/04 - 18 - [7.] Functional Description [7.1.] Analog interface The AK8859VQ accepts composite (CVBS) and S-Video (Y/C) signals, with 2 input pins available for this purpose. The decode signal is selected via the register. Input signal selection Sub Address: 0x00 [1:0] Name Definition Notes AINSEL0 ~ AINSEL1 [AINSEL1 : AINSEL0] [00]: AIN1 (CVBS) [01]: AIN2 (CVBS) [10]: AIN1(Y) / AIN2(C) (S-Video) [11]: No-signal input (Analog circuit is set to power-down*) *Clamp and ADC block is power-downed. In used with AINSEL[1:0]=[11], Ouput data is depend on NSIGMD[1:0]–bit. However, in used with NSIGMD[1:0]=[10], DATA[7:0]-pin, HD-pin, VD_F-pin, VAR-pin and VARSUB-pin output Low. [7.2.] Clock mode The AK8859VQ input clock can be selected between internal built crystal and external clock input via register setting. The input clock frequency is 24.576MHz. Clock mode setting Sub Address: 0x00 [7] Name Definition Notes CLKMD [0]: For crystal [1]: External clock input (clock generator) [7.3.] Analog clamp circuit The analog circuit of AK8859VQ clamps the input signal to the reference level. The way to clamp the input signal is show as follows. ○ When decode composite (CVBS) video signal Clamp timing is performs by sync tip clamp (analog sync tip clamp). The clamp timing pulse, with its origin at the falling edge of the internally synchronized and separated sync signal, is generated at approximately the central position of the sync signal. ○ When decode S-Video (Y/C) signal (Y signal): Clamp timing is performs by sync tip clamp (analog sync tip clamp). The clamp timing pulse, with its origin at the falling edge of the internally synchronized and separated sync signal, is generated at approximately the central position of the sync signal. (C signal): Clamp timing is performs by middle clamp (analog middle clamp). The clamp timing pulse is generated exactly at the same timing of Y signal clamp pulse. |
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