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AK8859VN Datasheet(PDF) 32 Page - Asahi Kasei Microsystems |
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AK8859VN Datasheet(HTML) 32 Page - Asahi Kasei Microsystems |
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32 / 72 page  [AK8859VN] MS1179-E-00 AKM Confidential 2010/04 - 32 - [7.22.2.2.] Fixed-clock mode In fixed-clock mode, the internal clock is not synchronized with the output signal, but a space of 122/132 (NTSC/PAL) pixels is guaranteed between the horizontal sync signal and the start of the active video interval. (For example, composite video signal input timing is shown below and 1pixel = 2CLK) 244CLK (264CLK) 128CLK 1440CLK 32CLK (24CLK) HD DVALID Video Signal Active video interval Fixed Not fixed Cb0 Cr0 Y0 Y1 Cb1 Y2 Cr1 Y3 Y719 Cr359 Y718 ······ ····· ·············· FF SAV [7.23] Digital Pixel interpolator The digital pixel interpolator of the AK8859VN aligns vertical pixel positions in both frame-lock and fixed-clock operating modes. The pixel interpolator can be set to ON or OFF via register. With a register setting of AUTO, the pixel interpolator is OFF or ON depending on the clock mode, as follows. Line-locked clock mode OFF Frame-locked clock mode ON Fixed-clock mode ON Settings for pixel interpolator operation Sub Address: 0x08 [5:4] Name Setting Value Interpolator operation Notes [00] Auto Dependent on clock mode. [01] ON [10] OFF INTPOL0 ~ INTPOL1 [11] Reserved |
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