HYS64(72)V4200/8220GU

SDRAM-Modules

Semiconductor Group

10

Notes:

1. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8 and

-8B and at 66 MHz for -10 modules. Input signals are changed once during tck, excepts for ICC6

and for standby currents when tck=infinity. All values are shown per memory component.

2. These parameters are measured with continous data stream during read access and all DQ

toggling. CL=3 and BL=4 assumed and the VDDQ current is excluded.

3. All AC characteristics are shown for device level.

An initial pause of 100

µs is required after power-up, then a Precharge All Banks command must

be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can

begin.

with the AC output load circuit show. Specified tac and toh parameters are measured with a 50

pF only, without any resistive termination and with a input signal of 1V / ns edge rate between

0.8V and 2.0 V.

6. Rated at 1.5 V

8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh

commands must be given to “wake-up“ the device.

9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after

CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied

once the Self Refresh Exit command is registered.

10.Referenced to the time which the output achieves the open circuit condition, not to output voltage

levels.

1.4V

1.4V

tSETUP

tHOLD

tAC

tAC

tLZ

tOH

tHZ

CLOCK

INPUT

OUTPUT

50 pF

I/O

Z=50 Ohm

+ 1.4 V

50 Ohm

2.4 V

0.4 V

fig.1

tCH

tCL

50 pF

I/O

Measurement conditions for

tac and toh