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AZT70 Datasheet(PDF) 8 Page - Arizona Microtek, Inc |
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AZT70 Datasheet(HTML) 8 Page - Arizona Microtek, Inc |
8 / 12 page Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC www.azmicrotek.com +1-480-962-5881 8 Request a Sample May 2012, Rev 1.2 t DA CLK bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit0 loaded 1st bit10 loaded last PV ≥ 0.6*V DD bit5 selected Resulting voltage if bit5 was high in EEPROM Resulting voltage if bit5 was low in EEPROM ≤ 0.4V indeterminate With an external 68k Ω resistor pull-up to V DD Figure 10 – Timing diagram to read bits from EEPROM ERASING THE EEPROM The EEPROM can be erased by initiating a programming cycle with all DA bits set high, including bit9 and bit10. After the programming cycle, all the EEPROM bits are set low (logical high) except for the check bit (bit0), which remains high. Table 5 – Erase sequence for EEPROM Step Action 1 Set the VDD supply voltage to +5.0V 2 Load the programming word bits all high. 3 Set the PV pin to +6V (≥5.6V, ≤6.1V) with the pulse and idle shown in timing diagram (Figure 11) 4 Verify the correct EEPROM contents by reading back the individual bits t DA CLK bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit0 loaded 1st bit10 loaded last PV 4µs min 10ms min EEPROM has been erased (no capacitors selected) ≥5.6V, ≤6.1V Figure 11 – Programming Sequence for erasing the EEPROM |
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