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CLRC663 Datasheet(PDF) 98 Page - NXP Semiconductors

Part No. CLRC663
Description  Contactless reader IC
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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CLRC663 Datasheet(HTML) 98 Page - NXP Semiconductors

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CLRC663
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.3 — 3 April 2012
171133
98 of 132
NXP Semiconductors
CLRC663
Contactless reader IC
9.13.3 PLL_Ctrl Register
The PLL_Ctrl register implements the control register for the IntegerN PLL. Two stages
exist to create the ClkOut signal from the 27,12MHz input. In the first stage the 27,12Mhz
input signal is multiplied by the value defined in PLLDiv_FB and divided by two, and the
second stage divides this frequency by the value defined by PLLDIV_Out.
9.13.4 PLLDiv_Out
Table 171. PLL_Ctrl register (address3Dh)
Bit
7
6
5
4
3
2
1
0
Symbol
ClkOutSel
ClkOut_En
PLL_PD
PLLDiv_FB
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Table 172. PLL_Ctrl register bits
Bit
Symbol
Description
7 to 4
CLkOutSel
0h - pin CLKOUT is used as I/O
1h - pin CLKOUT shows the output of the analog PLL
2h - pin CLKOUT is hold on 0
3h - pin CLKOUT is hold on 1
4h - pin CLKOUT shows 27.12 MHz from the crystal
5h - pin CLKOUT shows 13.56 MHz derived from the crystal
6h - pin CLKOUT shows 6.78 MHz derived from the crystal
7h - pin CLKOUT shows 3.39 MHz derived from the crystal
8h - pin CLKOUT is toggled by the Timer0 overflow
9h - pin CLKOUT is toggled by the Timer1 overflow
Ah - pin CLKOUT is toggled by the Timer2 overflow
Bh - pin CLKOUT is toggled by the Timer3 overflow
Ch...Fh - RFU
3
ClkOut_En
Enables the clock at Pin CLKOUT
2
PLL_PD
PLL power down
1-0
PLLDiv_FB
PLL feedback divider (see table 174)
Table 173. Setting of feedback divider PLLDiv_FB [1:0]
Bit 1
Bit 0
Division
0
0
23 (VCO frequency 312Mhz)
0
1
27 (VCO frequency 366MHz)
1
0
28 (VCO frequency 380Mhz)
1
1
23 (VCO frequency 312Mhz)
Table 174. PLLDiv_Out register (address 3Eh)
Bit
7
6
5
4
3
2
1
0
Symbol
PLLDiv_Out
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