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CLRC663 Datasheet(PDF) 94 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 94 Page - NXP Semiconductors |
94 / 132 page ![]() CLRC663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.3 — 3 April 2012 171133 94 of 132 NXP Semiconductors CLRC663 Contactless reader IC 9.12.3 RxWait Selects internal receiver settings. 9.12.4 RxThreshold Selects minimum threshold level for the bit decoder. 4 EGT_Check If set to 1, the EGT is checked and if it is too long a protocol error is set. (This is only valid for ISO/IEC14443 Type B) 3 EMD_Sup Enables the EMD suppression according ISO/IEC14443. If an error occurs within the first three bytes, these three bytes are assumed to be EMD, ignored and the FIFO is reset. A collision is treated as an error as well If a valid SOF was received, the EMD_Sup is set and a frame of less than 3 bytes had been received. RX_IRq is not set in this EMD error cases. If RxForceCRCWrite is set, the FIFO should not be read out before three bytes are written into. 2 to 0 Baudrate Defines the baud rate of the receiving signal. 2h: 26 kBd 3h: 52 kBd 4h: 106 kBd 5h: 212 kBd 6h: 424 kBd 7h: 847 kBd all remaining values are RFU Table 156. RxCtrl bits Bit Symbol Description Table 157. RxWait register (address 36h) Bit 7 6 5 4 3 2 1 0 Symbol RxWaitEtu RxWait Access rights r/w r/w Table 158. RxWait bits Bit Symbol Description 7 RXWaitEtu If set to 0, the RxWait time is RxWait 16/13.56 MHz If set to 1, the RxWait time is RxWait (0.5/DBFreq) 6 to 0 RxWait Defines the time after sending, where every input is ignored. Table 159. RxThreshold register (address 37h) Bit 7 6 5 4 3 2 1 0 Symbol MinLevel MinLevelP Access rights r/w r/w |
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