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CLRC663 Datasheet(PDF) 66 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 66 Page - NXP Semiconductors |
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66 / 132 page 
CLRC663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.3 — 3 April 2012 171133 66 of 132 NXP Semiconductors CLRC663 Contactless reader IC 9.4.3 FIFOLength Number of bytes in the FIFO buffer. In 512-bit modem this register is extended by FIFOControl.FifoLength. 9.4.4 FIFOData In- and output of FIFO buffer. Contrary to any read/write access to other addresses, reading or writing to the FIFO address does not increment the address pointer. Resulting in an efficient data transfer from and to the FIFO buffer. Writing to the FIFOData register increments, reading decrements the number of bytes present in the FIFO. 9.5 Interrupt configuration registers The Registers IRQ0 register and IRQ1 register implement a special functionality to avoid the not intended modification of bits. The mechanism of changing register contents requires the following consideration: IRQ(x). Set indicates, if a set bit on position 0 to 6 shall be cleared or set. Depending on the content of IRQ(x).Set, a write of a logical 1 to positions 0 to 6 either clears or sets the corresponding bit. With this register the application can modify the interrupt status which is maintained by the CLRC663 Bit 7 indicates, if the intended modification is a setting or clearance of a bit. Any 1 written to a bit position 6...0 will trigger the setting or clearance of this bit as defined by bit 7. Example: writing FFh sets all bits 6..0, writing 7Fh clears all bits 6..0 of the interrupt request register Table 55. FIFOLength register (address 04h); reset value: 00h Bit 7 6 5 4 3 2 1 0 Symbol FIFOLength Access rights dy Table 56. FIFOLength bits Bit Symbol Description 7 to 0 FIFOLength Indicates the number of bytes in the FIFO buffer. In 512-bit modem this register is extended by the bits FIFOLength in the FIFOControl register. Writing to the FIFOData register increments, reading decrements the number of bytes in the FIFO. Table 57. FIFOData register (address 05h); Bit 7 6 5 4 3 2 1 0 Symbol FIFOData Access rights dy Table 58. FIFOData bits Bit Symbol Description 7 to 0 FIFOData Data input and output port for the internal FIFO buffer. Refer to Section 8.5 “Buffer”. |
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