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CLRC663 Datasheet(PDF) 60 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 60 Page - NXP Semiconductors |
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60 / 132 page  CLRC663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.3 — 3 April 2012 171133 60 of 132 NXP Semiconductors CLRC663 Contactless reader IC 9. CLRC663 registers 9.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle, bits with same behavior are grouped in common registers. The access conditions are described in Table 45. Table 45. Behavior of register bits and their designation Abbreviation Behavior Description r/w read and write These bits can be written and read via the host interface. Since they are used only for control purposes, the content is not influenced by the state machines but can be read by internal state machines. dy dynamic These bits can be written and read via the host interface. They can also be written automatically by internal state machines, for example Command register changes its value automatically after the execution of the command. r read only These register bits indicates hold values which are determined by internal states only. w write only Reading these register bits always returns zero. RFU - These bits are reserved for future use and must not be changed. In case of a required write access, it is recommended to write a logic 0. Table 46. CLRC663 registers overview Address Register name Function 00h Command Starts and stops command execution 01h HostCtrl Host control register 02h FIFOControl Control register of the FIFO 03h WaterLevel Level of the FIFO underflow and overflow warning 04h FIFOLength Length of the FIFO 05h FIFOData Data In/Out exchange register of FIFO buffer 06h IRQ0 Interrupt register 0 07h IRQ1 Interrupt register 1 08h IRQ0En Interrupt enable register 0 09h IRQ1En Interrupt enable register 1 0Ah Error Error bits showing the error status of the last command execution 0Bh Status Contains status of the communication 0Ch RxBitCtrl Control register for anticollision adjustments for bit oriented protocols 0Dh RxColl Collision position register 0Eh TControl Control of Timer 0..3 0Fh T0Control Control of Timer0 10h T0ReloadHi High register of the reload value of Timer0 11h T0ReloadLo Low register of the reload value of Timer0 12h T0CounterValHi Counter value high register of Timer0 13h T0CounterValLo Counter value low register of Timer0 |
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