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CLRC663 Datasheet(PDF) 52 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 52 Page - NXP Semiconductors |
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52 / 132 page  CLRC663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.3 — 3 April 2012 171133 52 of 132 NXP Semiconductors CLRC663 Contactless reader IC 8.9 Power management 8.9.1 Supply concept The CLRC663 is supplied by VDD (Supply Voltage), PVDD (Pad Supply) and TVDD (Transmitter Power Supply). These three voltages are independent from each other. To connect the CLRC663 to a Microcontroller supplied by 3.3 V, PVDD and VDD shall be at a level of 3.3 V as well, TVDD can be in a range from 3.3 V to 5.0 V. A higher supply voltage at TVDD will result in a higher field strength. Independent of the voltage it is recommended to buffer these supplies with blocking capacitances close to the terminals of the package. VDD and PVDD are recommended to be blocked with a capacitor of 100 nF min, TVDD is recommended to be blocked with 2 capacitors, 100 nF parallel to 1.0 F AVDD and DVDD are not supply input pins. They are output pins and shall be connected to blocking capacitors 470 nF each. 8.9.2 Power reduction mode 8.9.2.1 Power-down A hard power-down is enabled with HIGH level on pin PDOWN. This turns off the internal 1.8 V voltage regulators for the analog and digital core supply as well as the oscillator. All digital input buffers are separated from the input pads and clamped internally (except pin PDOWN itself). The output pins are switched to high impedance. To leave the power-down mode the level at the pin PDOWN as to be set to LOW. This will start the internal start-up sequence. 8.9.2.2 Standby mode The standby mode is entered immediately after setting the bit PowerDown in the register Command. All internal current sinks are switched off except the LFO. Voltage references and voltage regulators will be set into stand-by mode. In opposition to the power-down mode, the digital input buffers are not separated by the input pads and keep their functionality. The digital output pins do not change their state. During standby mode, all registers values, the FIFO’s content and the configuration itself will keep its current content. To leave the standby mode the bit PowerDown in the register Command is cleared. This will trigger the internal start-up sequence. The reader IC is in full operation mode again when the internal start-up sequence is finalized (the typical duration is 15 us). Alternatively, a value of 55h can be sent to the CLRC663 using the RS232 interface to leave the standby mode. Then read accesses shall be performed at address 00h until the device returns the content of this address. The return of the content of address 00h indicates that the device is ready to receive further commands and the internal start-up sequence is finalized. 8.9.2.3 Modem off mode When the ModemOff bit in the register Control is set the antenna transmitter and the receiver are switched off. |
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