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CLRC663 Datasheet(PDF) 41 Page - NXP Semiconductors

Part No. CLRC663
Description  Contactless reader IC
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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CLRC663 Datasheet(HTML) 41 Page - NXP Semiconductors

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CLRC663
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.3 — 3 April 2012
171133
41 of 132
NXP Semiconductors
CLRC663
Contactless reader IC
8.6.3.2
Block diagram
Figure 28 shows the block diagram of the receiver circuitry. The receiving process
includes several steps. First the quadrature demodulation of the carrier signal of
13.56 MHz is done. Several tuning steps in this circuit are possible.
The receiver can also be operated in a single ended mode. In this case the
Rcv_RX_single has to be set. In the single ended use case two receiver pins RXP and
RXN need to be connected and will provide a single ended signal to the receiver circuitry.
When using the receiver in a single ended mode the reading distance will be decreased
compared to a double ended antenna implementation.
The quadrature-demodulator uses two different clocks, Q-clock and I-clock, with a phase
shift of 90
 between them. Both resulting baseband signals are amplified, filtered and
forwarded to a correlation circuitry.
The typical application is intended to implement the Fully differential mode and will deliver
maximum reader/writer distance. The Quasi differential mode can be used together with
dedicated antenna topologies that allow a reduction of matching components at the cost
of overall reading performance.
Fig 28. Block diagram of receiver circuitry
Table 29.
Configuration for single or differential receiver
Mode
rcv_rx_single
pins RXP and RXN
Fully differential
0
provide differential signal from
differential antenna by separate
rx-coupling branches
Quasi differential
1
connect RXP and RXN together
and provide single ended signal
from antenna by a single
rx-coupling branch
001aan358
13.56 MHz
I/O CLOCK
GENERATION
I-clks
Q-clks
clk_27 MHz
TIMING
GENERATION
ADC
DATA
DATA
Adc_data_ready
clk_27 MHz
mixer
mix_out_i_p
2-stage BBA
mix_out_i_n
out_i_p
out_i_n
rx_p
rx_n
rx_p
rx_n
mixer
mix_out_q_p
2-stage BBA
mix_out_q_n
out_q_p
out_q_n
rcv_gain<1:0>
rcv_hpcf<1:0>
fully/quasi-differential
fully/quasi-differential
rcv_gain<1:0>
rcv_hpcf<1:0>
rx_p
rx_n


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