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CLRC663 Datasheet(PDF) 28 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 28 Page - NXP Semiconductors |
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28 / 132 page  CLRC663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.3 — 3 April 2012 171133 28 of 132 NXP Semiconductors CLRC663 Contactless reader IC In order to support a fast FIFO data transfer, the address pointer is not incremented automatically in case the address is pointing to the FIFO. The read/write bit shall be set to logic 1. 8.4.4.9 I2CL-bus interface The CLRC663 provides an interface option according to of a logical handling of an I2C interface. This logical interface fulfills the I2C specification, but the rise/fall timings will not be according the I2C standard. Standard I/O pads are used for communication and the communication speed is limited to 5 MBaud. The protocol itself is equivalent to the fast mode protocol of I2C. The address is 01010xxb, where the last two bits of the address can be defined by the application. The definition of this bits can be done by two options. With a pin, where the higher bit is fixed to 0 or the configuration can be defined via EEPROM. Refer to the EEPROM configuration in Section 8.7. Fig 22. Register read and write access 001aam305 Ack 0 (W) Ack 0 SA I2C slave address A7-A0 CLRC663 register address A6-A0 Ack DATA [7..0] SO SO [0..n] Ack 0 (W) Ack Optional, if the previous access was on the same register address Read Cycle Write Cycle 0 SA I2C slave address A7-A0 CLRC663 register address A6-A0 1 (R) Ack SA sent by master sent by slave I2C slave address A7-A0 Ack DATA [7..0] SO [0..n] 0..n Nack DATA [7..0] Table 24. Timing parameter I2CL Parameter Min Max Unit fSCL 05MHz tHD;STA 80 - ns tLOW 100 - ns tHIGH 100 - ns |
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