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CLRC663 Datasheet(PDF) 26 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 26 Page - NXP Semiconductors |
26 / 132 page ![]() CLRC663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.3 — 3 April 2012 171133 26 of 132 NXP Semiconductors CLRC663 Contactless reader IC 8.4.4.5 I2C Acknowledge An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. The master can then generate either a STOP (P) condition to stop the transfer, or a repeated START (Sr) condition to start a new transfer. A master-receiver shall indicate the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter shall release the data line to allow the master to generate a STOP (P) or repeated START (Sr) condition. 8.4.4.6 I2C 7-bit addressing During the I2C-bus addressing procedure, the first byte after the START condition is used to determine which slave will be selected by the master. Fig 19. Acknowledge on the I2C- bus Fig 20. Data transfer on the I2C- bus 001aam302 clock pulse for acknowledgement 1 SCL FROM MASTER DATA OUTPUT BY RECEIVERER DATA OUTPUT BY TRANSMITTER 28 9 acknowledge START condition S not acknowledge 001aam303 MSB acknowledgement signal from slave acknowledgement signal from receiver clock line held low while interrupts are serviced byte complete, interrupt within slave 1 27 8 9 1 2 9 ACK ACK 3 - 8 Sr or P P Sr S or Sr |
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