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Product data sheet
Rev. 3.3 — 3 April 2012
26 of 132
Contactless reader IC
An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock
pulse is generated by the master. The transmitter of data, either master or slave, releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer, or a
repeated START (Sr) condition to start a new transfer.
A master-receiver shall indicate the end of data to the slave- transmitter by not generating
an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter
shall release the data line to allow the master to generate a STOP (P) or repeated START
I2C 7-bit addressing
During the I2C-bus addressing procedure, the first byte after the START condition is used
to determine which slave will be selected by the master.
Fig 19. Acknowledge on the I2C- bus
Fig 20. Data transfer on the I2C- bus
clock pulse for
signal from slave
signal from receiver
clock line held low while
interrupts are serviced
interrupt within slave
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