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CLRC663 Datasheet(PDF) 19 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 19 Page - NXP Semiconductors |
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19 / 132 page  CLRC663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.3 — 3 April 2012 171133 19 of 132 NXP Semiconductors CLRC663 Contactless reader IC 8.4.2 SPI interface 8.4.2.1 General The CLRC663 acts as a slave during the SPI communication. The SPI clock SCK has to be generated by the master. Data communication from the master to the slave uses the Line MOSI. Line MISO is used to send data back from the CLRC663 to the master. A serial peripheral interface (SPI compatible) is supported to enable high speed communication to a host. The implemented SPI compatible interface is according to a standard SPI interface. The SPI interface can handle data speed of up to 10 Mbit/s. In the communication with a host CLRC663 acts as a slave receiving data from the external host for register settings and to send and receive data relevant for the communication on the RF interface. On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI line shall be stable on rising edge of the clock line (SCK) and is allowed to change on falling edge. The same is valid for the MISO line. Data is provided by the CLRC663 on the falling edge and is stable on the rising edge.The polarity of the clock is low at SPI idle. 8.4.2.2 Read data To read out data from the CLRC663 by using the SPI compatible interface the following byte order has to be used. The first byte that is sent defines the mode (LSB bit) and the address. Table 14. Connection scheme for detecting the different interface types Pin Pin Symbol UART SPI I2C I2C-L 28 IF0 RX MOSI ADR1 ADR1 29 IF1 - SCK SCL SCL 30 IF2 TX MISO ADR2 SDA 31 IF3 1 NSS SDA ADR2 26 IFSEL0 0 0 1 1 27 IFSEL1 0 1 0 1 Fig 12. Connection to host with SPI 001aal998 READER IC IF1 SCK IF0 MOSI IF2 MISO IF3 NSS Table 15. Byte Order for MOSI and MISO byte 0 byte 1 byte 2 byte 3 to n-1 byte n byte n+1 MOSI address 0 address 1 address 2 …….. address n 00h MISO X data 0 data 1 …….. data n 1data n |
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