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CLRC663 Datasheet(PDF) 18 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 18 Page - NXP Semiconductors |
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CLRC663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.3 — 3 April 2012 171133 18 of 132 NXP Semiconductors CLRC663 Contactless reader IC 8.3.7.2 ISO/IEC 18092 framing and coding The ISO/IEC 18092 framing and coding in Passive communication mode is defined in the ISO/IEC 18092 standard. 8.3.7.3 ISO/IEC 18092 protocol support The ISO/IEC 18092 protocol is not described in this document. For a detailed explanation of the protocol, refer to the ISO/IEC 18092 standard. 8.3.8 EPC Class-1 HF and ICODE 8.3.8.1 Data encoding ICODE The ICODE protocols have mainly three different methods of data encoding: • “1” out of “4” coding scheme • “1” out of “256” coding scheme • “Return to Zero” (RZ) coding scheme. Data encoding for all three coding schemes is done by the ICODE generator. The supported EPC Class-1 HF modes are: • 2 pulse for 424 Kbit subcarrier • 4 pulse for 424 Kbit subcarrier • 2 pulse for 848 Kbit subcarrier • 4 pulse for 848 Kbit subcarrier 8.4 Host interfaces 8.4.1 Host interface configuration The CLRC663 supports direct interfacing of various hosts as the SPI, I2C, I2CL and serial UART interface type. The CLRC663 resets its interface and checks the current host interface type automatically having performed a power-up or resuming from power down. The CLRC663 identifies the host interface by the means of the logic levels on the control pins after the Cold Reset Phase. This is done by a combination of fixed pin connections.The following table shows the possible configurations defined by IFSEL1,IFSEL0: Table 13. Framing and coding overview Transfer speed Framing and Coding 106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme 212 kbit/s According to the FeliCa scheme 424 kbit/s According to the FeliCa scheme |
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