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HYB39S64160AT Datasheet(PDF) 7 Page - Siemens Semiconductor Group |
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HYB39S64160AT Datasheet(HTML) 7 Page - Siemens Semiconductor Group |
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7 / 53 page  Semiconductor Group 7 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. A0 - A11 Input Level — During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organisation: 16M x 4 SDRAM CAn = CA9 (Page Length = 1024 bits) 8M x 8 SDRAM CAn = CA8 (Page Length = 512 bits) 4M x 16 SDRAM CAn = CA7 (Page Length = 256 bits) In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. BA0,BA1 Input Level — Bank Select (BS) Inputs. Selects which bank is to be active. DQx Input Output Level — Data Input/Output pins operate in the same manner as on conventional DRAMs. DQM LDQM UDQM Input Pulse Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. One DQM input it present in x4 and x8 SDRAMs, LDQM and UDQM controls the lower and upper bytes in x16 SDRAMs. VDD,VSS Supply Power and ground for the input buffers and the core logic. VDDQ VSSQ Supply — — Isolated power supply and ground for the output buffers to provide improved noise immunity. |
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