Semiconductor Group

42

HYB 511000BJ/BJL-50/-60/-70

1 M

× 1-DRAM

Notes :

4) An initial pause of 200

µs is required after power-up followed by 8 RAS cycles before proper device operation

is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles

instead of 8 RAS cycles are required.

6) Measured with a load equivalent to 2 TTL loads and 100 pF.

output voltage levels.

9) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge

in read-write cycles.

electrical characteristics only.

cycle and DO will contain data read from the selected cell. If neither of the above sets of conditions is satisfied,

the condition of DO (at access time) is indeterminate.