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HYB39S64400AT-10 Datasheet(PDF) 8 Page - Siemens Semiconductor Group |
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HYB39S64400AT-10 Datasheet(HTML) 8 Page - Siemens Semiconductor Group |
8 / 53 page Semiconductor Group 8 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Note: 1. V = Valid, x = Don’t Care, L = Low Level, H = High Level 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BS0, BS1 signals. 4. Device state is Full Page Burst operation 5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock suspend mode. Operation Device State CKE n-1 CKE n CS RAS CAS WE DQM A0-9, A11 A10 BS0 BS1 Row Activate (ACT) Idle3 H X L L H H XVVV Read (READ) Active3 H X LHLH X V L V Read w/ Autoprecharge (READA) Active3 H X LHLH X V H V Write (WRITE) Active3 HX L H L L X V L V Write w/ Autoprecharge (WRITEA) Active3 HX L H L L X V H V Row Precharge (PRE) Any H X L L H L X X L V Precharge All (PREA) Any H X L L H L X X H X Mode Register Set (MRS) Idle H X LLLL XVVV No Operation (NOP) Any H X L H H H XXXX Device Deselect (INHBT) Any H X H X X XXXXX Auto Refresh (REFA) Idle H H L L L H XXXX Self Refresh Entry (REFS-EN) Idle H L L L L H XXXX Self Refresh Exit (REFS-EX) Idle (Self Refr.) LH H XXX XXXX LH H X Power Down Entry (PDN-EN) Idle Active5 HL H XXX XXXX LH H X Power Down Exit (PDN-EX) Any (Power Down) LH H XXX XXXX LH HL Data Write/Output Enable Active H XXXXX L X X X Data Write/Output Disable Active H XXXXX H X X X |
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