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HYB39S256400T-10 Datasheet(PDF) 4 Page - Siemens Semiconductor Group |
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HYB39S256400T-10 Datasheet(HTML) 4 Page - Siemens Semiconductor Group |
4 / 56 page HYB 39S256400/800/160T 256 MBit Synchronous DRAM Semiconductor Group 4 1998-10-01 Block Diagram for 64 M × 4 SDRAM (13/11/2 addressing) A0 - A9, A11, AP BA0, BA1 Column Addresses Address Buffer Column Address Counter Column A0 - A12, BA0, BA1 Row Addresses Row Address Buffer Counter Refresh 8196 x Bank 3 Decoder Array Memory Row Bank 2 8196 x Row Decoder Array Memory 2048 x 4 Bit 8196 x Bank 0 Bank 1 8196 x Row Memory Array Decoder Row Decoder Array Memory Input Buffer Output Buffer DQ0 - DQ3 Control Logic & Timing Generator CLK CKE CS RAS CAS WE DQM VREF*) *) on SSTL versions only SPB03781 2048 x 4 Bit 2048 x 4 Bit 2048 x 4 Bit |
Similar Part No. - HYB39S256400T-10 |
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