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S8866-64 Datasheet(PDF) 6 Page - Hamamatsu Corporation

Part No. S8866-64
Description  Photodiode array combined with signal processing IC
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Maker  HAMAMATSU [Hamamatsu Corporation]
Homepage  http://www.hamamatsu.com
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S8866-64 Datasheet(HTML) 6 Page - Hamamatsu Corporation

 
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Photodiode arrays with ampli er
S8866-64/-128
Timing chart
1 2 3
1 2 3
4 5 14 15 16 17
Video output
period
CLK
RESET
Video
Trig
EOS
tf(CLK)
tf(RESET)
tpw(CLK1)
t1
t2
tpw(RESET1)
tpw(RESET2)
tr(CLK)
tpw(RESET2)
18 19 20
12
n-1
n
tr(RESET)
tpw(RESET1)
20 clocks
8 clocks
8 clocks
Integration time
KMPDC0278EA
Parameter
Symbol
Min.
Typ.
Max.
Unit
Clock pulse width
tpw(CLK)
500
-
25000
ns
Clock pulse rise/fall times
tr(CLK), tf(CLK)
0
20
30
ns
Reset pulse width 1
tpw(RESET1)
21
-
-
CLK
Reset pulse width 2
tpw(RESET2)
20
-
-
CLK
Reset pulse rise/fall times
tr(RESET), tf(RESET)
0
20
30
ns
Clock pulse-reset pulse timing 1
t1
-20
0
20
ns
Clock pulse-reset pulse timing 2
t2
-20
0
20
ns
1. The internal timing circuit starts operation at the falling edge of CLK immediately after a RESET pulse goes Low.
2. When the falling edge of each CLK is counted as "1 clock", the video signal of the 1st channel appears between "18.5 clocks and 20
clocks". Subsequent video signals appear every 4 clocks.
3. To obtain video signals, extend the High period 3 clocks from the falling edge of CLK immediately after the RESET pulse goes Low,
to a 20 clock period.
4. The trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. The rising edge of each trigger
pulse is the recommended timing for data acquisition.
5. Signal charge integration time equals the High period of a RESET pulse. However, the charge integration does not start at the rise
of a RESET pulse but starts at the 8th clock after the rise of the RESET pulse and ends at the 8th clock after the fall of the RESET
pulse. After the RESET pulse next changes from High to Low, signals integrated within this period are sequentially read out as time-
series signals by the shift register operation. The rise and fall of a RESET pulse must be synchronized with the rise of a CLK pulse,
but the rise of a RESET pulse must be set outside the video output period. One cycle of RESET pulses cannot be set shorter than
the time equal to "36.5 + 4 × N (number of elements)" clocks.
6. The video signal after an EOS signal output becomes a high impedance state, and the video output will be inde nite.
6
S8866-64


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