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HYB39S16400BT-10 Datasheet(PDF) 7 Page - Siemens Semiconductor Group |
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HYB39S16400BT-10 Datasheet(HTML) 7 Page - Siemens Semiconductor Group |
7 / 64 page Semiconductor Group 7 HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM Block Diagram for HYB39S16160BT (2 banks x 512k x 16 SDRAM) Column Decoder and DQ Gate Sense Amplifiers Data Latches Data Latches 8 8 Column Decoder and DQ Gate Sense Amplifiers Column Decoder and DQ Gate Sense Amplifiers Memory Bank A 2048 x 512 Data Latches Data Latches 8 8 Column Decoder and DQ Gate Sense Amplifiers 8 CKE Buffer CLK Buffer CS Buffer RAS Buffer CAS Buffer WE Buffer DQM Buffer CKE CLK CS RAS CAS UDQM WE Mode Register Refresh Clock Row Address Counter Self A1 A2 A3 A4 A5 A6 A7 A10 A8 A9 A0 A11 (BS) 12 12 Sequential Control Bank A Row/Column Select Bank A Predecode A Column Decoder and DQ Gate Sense Amplifiers Sequential Control Bank B Predecode B 8 Row/Column Select Bank B 3 11 3 11 11 16 16 16 16 16 16 Memory Bank A 2048 x 256 2048 Data Latches Data Latches 8 Column Decoder and DQ Gate Sense Amplifiers Memory Bank B 2048 x 1024 Memory Bank B 2048 x 512 Memory Bank B 2048 x 1024 Memory Bank B 2048 x 256 2048 DQM Buffer LDQM 16 DQ1 DQ2 DQ3 DQ4 DQ5 DQ0 DQ6 DQ7 DQ9 DQ10 DQ11 DQ12 DQ13 DQ8 DQ14 DQ15 |
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