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HYB39S16400 Datasheet(PDF) 1 Page - Siemens Semiconductor Group

Part No. HYB39S16400
Description  16 MBit Synchronous DRAM
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Manufacturer  SIEMENS [Siemens Semiconductor Group]
Direct Link  http://www.siemens.com/
Logo SIEMENS - Siemens Semiconductor Group

HYB39S16400 Datasheet(HTML) 1 Page - Siemens Semiconductor Group

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Semiconductor Group
1
1998-10-01
16 MBit Synchronous DRAM
(second generation)
Advanced Information
The HYB 39S1640x/80x/16xAT are dual bank Synchronous DRAM’s based on the die revisions “B”
and “C” and organized as 2 banks
× 2MBit × 4, 2 banks × 1MBit × 8 and 2 banks × 512 kBit × 16
respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated with SIEMENS advanced 16 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to
125 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3 V
± 0.3 V power supply and are available in TSOPII packages.
• High Performance:
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• 0 to 70
°C operating temperature
• Dual Banks controlled by A11 (Bank Select)
• Programmable CAS Latency: 1, 2, 3
• Programmable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential type
1, 2, 4, 8 for Interleave type
CAS latency = 3
-8
-10
Units
f
CK
125
100
MHz
t
CK3
810
ns
t
AC3
78
ns
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read/Write control (
× 4, × 8)
• Dual Data Mask for byte control (
× 16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 4096 refresh cycles/64 ms
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V
± 0.3 V Power Supply
• LVTTL Interface versions
• Plastic Packages:
P-TSOPII-44-1 400 mil width (
× 4, × 8)
P-TSOPII-50-1 400 mil width (
× 16)
HYB 39S16400/800/160AT-8/-10


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