71M6534 datasheet(6/132 Pages) MAXIM | Exceeds IEC 62053/ANSI C12.20 Standards

6 / 132 page

71M6533/G/H and 71M6534/H Data Sheet

FDS_6533_6534_004

Rev 2

Tables

Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV[3:0] = 7)........... 11

Table 2: ADC Resolution .......................................................................................................................11

Table 3: ADC RAM Locations ................................................................................................................12

Table 4: XRAM Locations for ADC Results ............................................................................................15

Table 5: Inputs Selected in Regular and Alternate Multiplexer Cycles..................................................... 15

Table 6: CKMPU Clock Frequencies......................................................................................................19

Table 7: Memory Map............................................................................................................................20

Table 9: Special Function Register Map.................................................................................................21

Table 10: Generic 80515 SFRs - Location and Reset Values .................................................................22

Table 11: PSW Bit Functions (SFR 0xD0)...............................................................................................23

Table 12: Port Registers ........................................................................................................................24

Table 13: Stretch Memory Cycle Width..................................................................................................25

Table 14: 71M6533/71M6534 Specific SFRs .........................................................................................25

Table 16: UART Modes .........................................................................................................................27

Table 18: The S1CON (UART1) Register (SFR 0x9B).............................................................................28

Table 19: PCON Register Bit Description (SFR 0x87).............................................................................28

Table 20: Timers/Counters Mode Description ........................................................................................29

Table 21: Allowed Timer/Counter Mode Combinations...........................................................................29

Table 22: TMOD Register Bit Description (SFR 0x89) ............................................................................29

Table 23: The TCON Register Bit Functions (SFR 0x88) ........................................................................30

Table 24: The IEN0 Bit Functions (SFR 0xA8)........................................................................................31

Table 25: The IEN1 Bit Functions (SFR 0xB8) .......................................................................................31

Table 26: The IEN2 Bit Functions (SFR 0x9A)........................................................................................31

Table 27: TCON Bit Functions (SFR 0x88) .............................................................................................32

Table 28: The T2CON Bit Functions (SFR 0xC8)...................................................................................32

Table 29: The IRCON Bit Functions (SFR 0xC0) ....................................................................................32

Table 30: External MPU Interrupts.........................................................................................................33

Table 31: Interrupt Enable and Flag Bits ................................................................................................33

Table 32: Interrupt Priority Level Groups................................................................................................34

Table 33: Interrupt Priority Levels ..........................................................................................................34

Table 35: Interrupt Polling Sequence .....................................................................................................35

Table 36: Interrupt Vectors ....................................................................................................................35

Table 37: Clock System Summary.........................................................................................................37

Table 38: Bank Switching with FL_BANK[2:0] ........................................................................................41

Table 39: Data/Direction Registers and Internal Resources for DIO 1-15................................................43

Table 40: Data/Direction Registers and Internal Resources for DIO 16-30.............................................. 43

Table 41: Data/Direction Registers and Internal Resources for DIO 36-47.............................................. 44

Table 45: EECTRL Bits for the 3-wire Interface.......................................................................................48

Table 46: SPI Registers.........................................................................................................................50

Table 47: SPI Command Description .....................................................................................................51

Table 49: TMUX[4:0] Selections ............................................................................................................54

Table 50: Available Circuit Functions .....................................................................................................58

Table 51: VREF Definition for the Regular Accuracy Parts .....................................................................70

Table 52: VREF Definition for the High-Accuracy Parts..........................................................................70

Table 53: I/O RAM Map – Functional Order ...........................................................................................79

Table 54: I/O RAM Description – Alphabetical (by Bit Name) .................................................................83

Table 55: CE EQU[2:0] Equations and Element Input Mapping..............................................................97

Table 56: CE Raw Data Access Locations .............................................................................................97

Table 57: CESTATUS (CE RAM 0x80) Bit Definitions ..............................................................................98

Table 59: Sag Threshold and Gain Adjust Control................................................................................100

Table 60: CE Transfer Variables..........................................................................................................100

Table 61: CE Energy Measurement Variables......................................................................................101

Table 62: Other Transfer Variables ......................................................................................................102

Table 63: CE Temperature Registers...................................................................................................102

Table 65: CE Parameters for Noise Suppression and Code Version.....................................................104

Table 66: CE Calibration Parameters...................................................................................................104

Table 67: Absolute Maximum Ratings..................................................................................................107

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