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71M6534 Datasheet(PDF) 53 Page - Maxim Integrated Products |
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71M6534 Datasheet(HTML) 53 Page - Maxim Integrated Products |
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53 / 132 page  FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Rev 2 53 V3P3 V3P3 - 400mV V3P3 - 10mV VBIAS 0V Battery modes Normal operation, WDT enabled WDT dis- abled V1 A15 A14 A1 A0 C0 0 31 x D7 D6 D1 D0 D7 D6 D1 D0 C5 C6 C7 x PCSZ PSCK PSDI PSDO 8 bit CMD 16 bit Address DATA[ADDR] DATA[ADDR+1] 7 8 23 24 32 39 Extended Read . . . SERIAL READ A15 A14 A1 A0 C0 0 31 C5 C6 C7 x PCSZ PSCK PSDI PSDO 8 bit CMD 16 bit Address DATA[ADDR] DATA[ADDR+1] 7 8 23 24 32 39 Extended Write . . . SERIAL WRITE D7 D6 D1 D0 D7 D6 D1 D0 x HI Z HI Z (From Host) (From 653X) (From Host) (From 653X) Figure 16: SPI Slave Port: Typical Read and Write Operations SFR locations, i.e. the control registers internal to the 71M653x MPU, are not accessible via the SPI port. In cases where these registers have to be accessed, for example to control DIO pins, a protocol that uses the MPU has to be used for read and write operations involving the SFRs. 1.5.12 Hardware Watchdog Timer An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6533/71M6534. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds. When not refreshed on time, the WDT overflows and the part is reset as if the RESET pin were pulled high, except that the I/O RAM bits will be in the same state as after a wake-up from SLEEP or LCD modes (see the I/O RAM description in Section 5.2 for a list of I/O RAM bit states after RESET and wake-up). 4100 oscillator cycles (or 125 ms) after the WDT overflow, the MPU will be launched from program address 0x0000. A status bit, WD_OVF, is set when the WDT overflow occurs. This bit is preserved in LCD mode (not in SLEEP mode) and can be read by the MPU when WAKE rises to determine if the part is initializing after a WDT overflow event or after a power-up. After it is read, the MPU firmware must clear WD_OVF. The WD_OVF bit is also cleared by the RESET pin. There is no internal digital state that deactivates the WDT. The WDT can be disabled by tying the V1 pin to V3P3 (see Figure 17). Of course, this also deactivates V1 power fault detection. Since there is no method in firmware to disable the crystal oscillator or the WDT, it is guaranteed that whatever state the part might find itself in, upon watchdog overflow, the part will be reset to a known state. Figure 17: Functions Defined by V1 Asserting ICE_E will also deactivate the WDT. This is the only method that will work in BROWNOUT mode. In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer is also reset when the internal signal WAKE=0 (see Section 2.5 Wake Up Behavior). |
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