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71M6534 Datasheet(PDF) 50 Page - Maxim Integrated Products

Part No. 71M6534
Description  Exceeds IEC 62053/ANSI C12.20 Standards
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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71M6534 Datasheet(HTML) 50 Page - Maxim Integrated Products

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71M6533/G/H and 71M6534/H Data Sheet
FDS_6533_6534_004
50
Rev 2
1.5.11 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
locations. It is also able to send commands to the MPU. The interface to the slave port consists of the
PCSZ, PCLK, PSDI and PSDO pins. These pins are multiplexed with the LCD segment driver pins SEG3
to SEG6. The port pins default to LCD driver pins. The port is enabled by setting the SPE bit.
Possible applications for the SPI interface are:
1) An external host reads data from CE locations to obtain metering information. This can be used in
applications where the 71M6533 or 71M6534 function as a smart front-end with preprocessing
capability. Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE,
MPU, I/O RAM, but not SFRs or the 80515-internal register bank.
2) A communication link can be established via the SPI interface: By writing into MPU memory
locations, the external host can initiate and control processes in the 71M6533/71M6534 MPU.
Writing to a CE or MPU location normally generates an interrupt, a function that can be used to signal
to the MPU that the byte that had just been written by the external host must be read and processed.
Data can also be inserted by the external host without generating an interrupt.
3) An external DSP can access front-end data generated by the ADC. This mode of operation uses the
71M6533 or 71M6534 as an analog front-end (AFE).
A typical SPI transaction is as follows: While PCSZ is high, the port is held in an initialized/reset state.
During this state, PSDO is held in HiZ state and all transitions on PCLK and PSDI are ignored. When
PCSZ falls, the port will begin the transaction on the first rising edge of PCLK. The transaction ends
when PCSZ is raised. At this point, the SPI interrupt is generated. Some transactions may consist of a
command only. The read transaction consists of the following parts:
1. 8-bit command word generated by the host
2. 16-bit address generated by the host
3. 8-bit datum provided by the slave (71M653x)
4. Optionally, more 8-bit data bytes (71M653x)
The write transaction consists of the following parts:
1. 8-bit command word generated by the host
2. 16-bit address generated by the host
3. 8-bit datum provided by the host
4. Optionally, more 8-bit data bytes provided by the host
The optional data bytes are part of an auto-increment mode, where the read or write address is
incremented by 1 after every read or write operation and does not have to be generated by the host. This
operation mode is useful for quickly accessing fields of adjacent data in one long SPI command
sequence.
Table 46 lists I/O RAM registers (bit fields) that are involved in SPI transactions.
Table 46: SPI Registers
Register Name
Description
SP_ADDR[15:8]
SP_ADDR[7:0]
SPI Address. 16-bit address from the bus master. This register does not auto-incre-
ment and reading this register will not reflect the next available address after an auto-
increment command.
SP_CMD
SPI command. 8-bit command from the bus master.
SPE
SPI port enable. Enables the SPI interface.
SPI_FLAG
SPI interrupt flag. The flag is set by the hardware and is cleared by the firmware writ-
ing a 0. Firmware using this interrupt should clear the spurious interrupt indication
during initialization.
In order to allow access from the external host, the SPE bit has to be set. The SP_CMD and
SP_ADDR[15:0] bit fields contain a copy of the command word and address sent by the SPI master.


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