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71M6534 Datasheet(PDF) 48 Page - Maxim Integrated Products

Part No. 71M6534
Description  Exceeds IEC 62053/ANSI C12.20 Standards
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

71M6534 Datasheet(HTML) 48 Page - Maxim Integrated Products

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71M6533/G/H and 71M6534/H Data Sheet
FDS_6533_6534_004
48
Rev 2
Status
Bit
Name
Read/
Write
Reset
State Polarity Description
0110
Receive the last byte from the
EEPROM and do not send ACK.
1001
Issue a START sequence.
Others
No operation, set the ERROR bit.
The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. In
this case, a resistor has to be used in series with SDA to avoid data collisions due to limits in the
speed at which the SDA pin can be switched from output to input. However, controlling DIO4 and
DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too
busy to process interrupts.
Three-wire (µ-Wire) EEPROM Interface
A 500 kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is
selected by setting DIO_EEX[1:0] = 2. The EECTRL bits when the three-wire interface is selected are
shown in Table 45. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM
or read from the EEPROM, depending on the values of the EECTRL bits.
The µ-Wire EEPROM interface is only functional when MPU_DIV[2:0] = 000.
Table 45: EECTRL Bits for the 3-wire Interface
Control
Bit
Name
Read/
Write Description
7
WFR
W
Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed
until a rising edge is seen on the data line. This bit can be used during
the last byte of a Write command to cause the INT5 interrupt to occur
when the EEPROM has finished its internal write sequence. This bit is
ignored if HiZ=0.
6
BUSY
R
Asserted while the serial data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
5
HiZ
W
Indicates that the SD signal is to be floated to high impedance immediately
after the last SCK rising edge.
4
RD
W
Indicates that EEDATA is to be filled with data from EEPROM.
3:0
CNT[3:0]
W
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data will be read MSB first, and right
justified into the low order bits of EEDATA. If RD=0, CNT bits will be
sent MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA will simply obey the HiZ bit.
The timing diagrams in Figure 10 through Figure 14 describe the 3-wire EEPROM interface behavior. All
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 10 through Figure 14
are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM
will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should
then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to
a low-Z state.


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