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71M6534 Datasheet(PDF) 37 Page - Maxim Integrated Products |
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71M6534 Datasheet(HTML) 37 Page - Maxim Integrated Products |
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37 / 132 page  FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Rev 2 37 1.5 On-Chip Resources 1.5.1 Oscillator The 71M6533/71M6534 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do not require a high-current oscillator circuit. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery attached to VBAT. Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to Section 1.5.3 Real-Time Clock (RTC) for more information. The oscillator is powered directly and only from VBAT, which therefore must be connected to a DC voltage source. The oscillator requires approximately 100 nA, which is negligible compared to the internal leakage of a battery. The oscillator may appear to work when VBAT is not connected, but this mode of operation is not recommended. If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset. Therefore, an unexpected reset during a battery test should be interpreted as a battery failure. 1.5.2 PLL and Internal Clocks Timing for the device is derived from the 32.768 kHz crystal oscillator output. On-chip timing functions include: • The MPU clock (CKMPU) • The emulator clock (2 x CKMPU) • The clock for the CE (CKCE) • The clock driving the delta-sigma ADC along with the FIR (CKADC, CKFIR) • A real time clock (RTC). The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see Timers and Counters). Table 37 provides a summary of the clock functions provided. Table 37: Clock System Summary Clock Derived From MCK Divider / [M40MHZ, M26MHZ] Brownout Mode ÷ 2 / [1,0] ÷ 3 / [0,1] ÷ 4** / [0,0] 32 kHz CKPLL Crystal 78.6432 MHz 78.6432 MHz 78.6432 MHz Off MCK CKPLL 39.3216 MHz 26.2144 MHz 19.6608 MHz 112 kHz CKCE MCK 4.9152 MHz † 9.8304 MHz † 6.5536 MHz 4.9152 MHz Off CKADC / CKFIR MCK 4.9152 MHz 6.5536 MHz 4.9152 MHz 28 kHz CKMPU maximum MCK 9.8304 MHz*** 6.5536 MHz *** 4.9152 MHz *** 28 kHz CK32 MCK 32.768 kHz 32.768 kHz 32.768 kHz ** Default state at power-up *** This is the maximum CKMPU frequency. CKMPU can be reduced from this rate using MPU_DIV[2:0]. † CKCE = 9.8304 MHz when CE10MHZ is set, 4.9152 MHz otherwise. The master clock, MCK, is generated by an on-chip PLL that multiplies the crystal oscillator output frequency (CK32) by 2400 to provide 80 MHz (78.6432 MHz). A divider controlled by the I/O RAM registers M40MHZ and M26MHZ permits scaling of MCK by ½, ⅓, and ¼. All other clocks are derived from this scaled MCK output (making them multiples of 32768 Hz), and the clock skew is matched so that the rising edges of CKADC, CKCE, CK32, and CKMPU are aligned. |
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