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71M6534 Datasheet(PDF) 34 Page - Maxim Integrated Products

Part No. 71M6534
Description  Exceeds IEC 62053/ANSI C12.20 Standards
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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71M6534 Datasheet(HTML) 34 Page - Maxim Integrated Products

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71M6533/G/H and 71M6534/H Data Sheet
FDS_6533_6534_004
34
Rev 2
Interrupt Enable
Interrupt Flag
Interrupt Description
Name
Location
Name
Location
EX_XFER
2002[0]
IE_XFER
SFR E8[0]
XFER_BUSY interrupt (INT 6)
EX_RTC
2002[1]
IE_RTC
SFR E8[1]
RTC_1SEC interrupt (INT 6)
IEN_WD_NROVF 20B0[0]
WD_NROVF_FLAG 20B1[0]
WDT near overflow (INT 6)
IEN_SPI
20B0[4]
SPI_FLAG
20B1[4]
SPI Interface (INT2)
EX_FWCOL
2007[4]
IE_FWCOL0
SFR E8[3]
FWCOL0 interrupt (INT 2)
IE_FWCOL1
SFR E8[2]
FWCOL1 interrupt (INT 2)
EX_PLL
2007[5]
IE_PLLRISE
SFRE8[6]
PLL_OK rise interrupt (INT 4)
IE_PLLFALL
SFRE8[7]
PLL_OK fall interrupt (INT 4)
IE_WAKE
SFRE8[5]
AUTOWAKE flag
IE_PB
SFRE8[4]
PB flag
The AUTOWAKE and PB flag bits are shown in Table 31 because they behave similarly to interrupt flags,
even though they are not actually related to an interrupt. These bits are set by hardware when the MPU
wakes from a push button or wake timeout. The bits are reset by writing a zero. Note that the PB flag is
set whenever the PB is pushed, even if the part is already awake.
WD_NROVF_FLAG is set approximately 1 ms before a WDT reset occurs. The flag can be cleared by
writing a zero to it and is automatically cleared by the falling edge of WAKE.
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 32:
Table 32: Interrupt Priority Level Groups
Group Members
0
External interrupt 0, Serial
channel 1 interrupt
1
Timer 0 interrupt, External
interrupt 2
2
External interrupt 1, External
interrupt 3
3
Timer 1 interrupt, External
interrupt 4
4
Serial channel 0 interrupt,
External interrupt 5
5
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 33) by setting or clearing one bit in the SFR interrupt priority register IP0 and one in IP1 (Table 34).
If requests of the same priority level are received simultaneously, an internal polling sequence as shown
in Table 35 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 33: Interrupt Priority Levels
IP1[x]
IP0[x]
Priority Level
0
0
Level 0 (lowest)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest)


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