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71M6534 Datasheet(PDF) 33 Page - Maxim Integrated Products

Part No. 71M6534
Description  Exceeds IEC 62053/ANSI C12.20 Standards
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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71M6534 Datasheet(HTML) 33 Page - Maxim Integrated Products

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FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
Rev 2
33
External MPU Interrupts
The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in
other parts of the 71M6533/71M6534, for example the CE, DIO, RTC, EEPROM interface.
The external interrupts are connected as shown in Table 30. The polarity of interrupts 2 and 3 is
programmable in the MPU via the I3FR and I2FR bits in T2CON. Interrupts 2 and 3 should be programmed
for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts 4 through 6
are defined as rising-edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted
to achieve the edge polarity shown in Table 30.
Table 30: External MPU Interrupts
External
Interrupt
Connection
Polarity
Flag Reset
0
Digital I/O High Priority
see Section 1.5.7
automatic
1
Digital I/O Low Priority
see Section 1.5.7
automatic
2
FWCOL0, FWCOL1, SPI
falling
automatic
3
CE_BUSY
falling
automatic
4
PLL_OK (rising), PLL_OK (falling)
rising
automatic
5
EEPROM busy
falling
automatic
6
XFER_BUSY, RTC_1SEC or WD_NROVF falling
manual
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See Section
1.5.7 Digital I/O for more information.
FWCOLx interrupts occur when the CE collides with a flash write attempt. See the flash write description
in the Flash Memory section for more detail.
SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own
flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY,
RTC_1SEC, WD_NROVF, FWCOL0, FWCOL1, SPI, PLLRISE and PLLFALL have their own enable and
flag bits in addition to the interrupt 6, 4 and enable and flag bits (see Table 31).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other
flags, IE_XFER through IE_PB, are cleared by writing a zero to them.
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided. The hardware implements bit operations as a
byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
the write, its flag will be cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a
zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 31: Interrupt Enable and Flag Bits
Interrupt Enable
Interrupt Flag
Interrupt Description
Name
Location
Name
Location
EX0
SFR A8[0]
IE0
SFR 88[1]
External interrupt 0
EX1
SFR A8[2]
IE1
SFR 88[3]
External interrupt 1
EX2
SFR B8[1]
IEX2
SFR C0[1]
External interrupt 2
EX3
SFR B8[2]
IEX3
SFR C0[2]
External interrupt 3
EX4
SFR B8[3]
IEX4
SFR C0[3]
External interrupt 4
EX5
SFR B8[4]
IEX5
SFR C0[4]
External interrupt 5
EX6
SFR B8[5]
IEX6
SFR C0[5]
External interrupt 6


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