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71M6534 Datasheet(PDF) 31 Page - Maxim Integrated Products

Part No. 71M6534
Description  Exceeds IEC 62053/ANSI C12.20 Standards
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

71M6534 Datasheet(HTML) 31 Page - Maxim Integrated Products

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FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
Rev 2
31
is terminated by a return from instruction, RETI. When an RETI is performed, the processor will return to
the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is
set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt
will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following
conditions are met:
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 24, Table 25 and Table 26).
The Timer/Counter control registers, TCON and T2CON (see Table 27 and Table 28).
The interrupt request register, IRCON (see Table 29).
The interrupt priority registers: IP0 and IP1 (see Table 34).
Table 24: The IEN0 Bit Functions (SFR 0xA8)
Bit
Symbol Function
IEN0[7]
EAL
EAL = 0 disables all interrupts.
IEN0[6]
WDT
Not used for interrupt control.
IEN0[5]
Not Used.
IEN0[4]
ES0
ES0 = 0 disables serial channel 0 interrupt.
IEN0[3]
ET1
ET1 = 0 disables timer 1 overflow interrupt.
IEN0[2]
EX1
EX1 = 0 disables external interrupt 1.
IEN0[1]
ET0
ET0 = 0 disables timer 0 overflow interrupt.
IEN0[0]
EX0
EX0 = 0 disables external interrupt 0.
Table 25: The IEN1 Bit Functions (SFR 0xB8)
Bit
Symbol Function
IEN1[7]
Not used.
IEN1[6]
Not used.
IEN1[5]
EX6
EX6 = 0 disables external interrupt 6: XFER_BUSY, RTC_1SEC, WD_NROVF
IEN1[4]
EX5
EX5 = 0 disables external interrupt 5: EEPROM_BUSY
IEN1[3]
EX4
EX4 = 0 disables external interrupt 4: PLL_OK (rise), PLL_OK (fall)
IEN1[2]
EX3
EX3 = 0 disables external interrupt 3: CE_BUSY
IEN1[1]
EX2
EX2 = 0 disables external interrupt 2: FWCOL0, FWCOL1, SPI
IEN1[0]
Not Used.
Table 26: The IEN2 Bit Functions (SFR 0x9A)
Bit
Symbol Function
IEN2[0]
ES1
ES1 = 0 disables the serial channel 1 interrupt.


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