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71M6534 Datasheet(PDF) 30 Page - Maxim Integrated Products

Part No. 71M6534
Description  Exceeds IEC 62053/ANSI C12.20 Standards
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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71M6534 Datasheet(HTML) 30 Page - Maxim Integrated Products

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71M6533/G/H and 71M6534/H Data Sheet
FDS_6533_6534_004
30
Rev 2
timer.
TMOD[5:4]
M1:M0
Selects the mode for Timer/Counter 1 as shown in Table 20.
Timer/Counter 0
TMOD[3]
Gate
If TMOD[3] is set, external input signal control is enabled for Counter 0.
external gate control. The TR0 bit in the TCON register (SFR 0x88) must
also be set in order for Counter 0 to increment.
With these settings Counter 0 is incremented on every falling edge of the
logic signal applied to one or more of the interrupt sources controlled by
the DI_RBP, DIO_R1, … DIO_RXX registers.
TMOD[2]
C/T
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as
a timer.
TMOD[1:0]
M1:M0
Selects the mode for Timer/Counter 0, as shown in Table 20.
Table 23: The TCON Register Bit Functions (SFR 0x88)
Bit
Symbol
Function
TCON[7]
TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when
an interrupt is processed.
TCON[6]
TR1
Timer 1 run control bit. If cleared, Timer 1 stops.
TCON[5]
TF0
Timer 0 overflow flag set by hardware when Timer 0 overflows. This
flag can be cleared by software and is automatically cleared when an
interrupt is processed.
TCON[4]
TR0
Timer 0 Run control bit. If cleared, Timer 0 stops.
TCON[3]
IE1
Interrupt 1 edge flag is set by hardware when the falling edge on external
pin int1 is observed. Cleared when an interrupt is processed.
TCON[2]
IT1
Interrupt 1 type control bit set by the MPU. Selects either the falling
edge or low level on input pin to cause an external interrupt.
TCON[1]
IE0
Interrupt 0 edge flag is set by hardware when the falling edge on external
pin int0 is observed. Cleared when an interrupt is processed.
TCON[0]
IT0
Interrupt 0 type control bit. Selects either the falling edge or low level
on input pin to cause interrupt.
1.4.8 WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard watchdog timer instead (see Section
1.5.12 Hardware Watchdog Timer).
1.4.9 Interrupts
The 80515 MPU provides 11 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0 (SFR 0xA8),
IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A). shows the device interrupt structure.
Referring to Figure 7, interrupt sources can originate from within the 80515 MPU core (referred to as
Internal Sources) or can originate from other parts of the 71M653x SoC (referred to as External Sources).
There are seven external interrupt sources, as seen in the leftmost part of Figure 7, and in Table 24 and
Table 25 (i.e. EX0-EX6)
Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 36. Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service


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