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71M6534 Datasheet(PDF) 26 Page - Maxim Integrated Products |
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71M6534 Datasheet(HTML) 26 Page - Maxim Integrated Products |
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26 / 132 page  71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 26 Rev 2 Register (Alternate Name) SFR Address Bit Field Name R/W Description IFLAGS 0xE8[0] IE_XFER R/W This flag monitors the XFER_BUSY interrupt. It is set by hardware and must be cleared by the interrupt handler. 0xE8[1] IE_RTC R/W This flag monitors the RTC_1SEC interrupt. It is set by hardware and must be cleared by the interrupt handler. 0xE8[2] FW_COL1 R/W This flag indicates that a flash write was in progress while the CE was busy. 0xE8[3] FW_COL0 R/W This flag indicates that a flash write was attempted when the CE was attempting to begin a code pass. 0xE8[4] IE_PB R/W This flag indicates that the wake-up pushbutton was pressed. 0xE8[5] IE_WAKE R/W This flag indicates that the MPU was awakened by the autowake timer. 0xE8[6] PLL_RISE R/W PLL_RISE Interrupt Flag: Write 0 to clear the PLL_RISE interrupt flag. 0xE8[7] PLL_FALL R/W PLL_FALL Interrupt Flag: Write 0 to clear the PLL_FALL interrupt flag. INTBITS (INT0 … INT6) 0xF8[6:0] INT6 … INT0 R Interrupt inputs. The MPU may read these bits to see the status of external interrupts INT0 up to INT6. These bits do not have any memory and are primarily intended for debug use. 0xF8[7] WD_RST W The WDT is reset when a 1 is written to this bit. Only byte operations on the entire INTBITS register should be used when writing. The byte must have all bits set except the bits that are to be cleared. 1.4.5 Instruction Set All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated op-codes is contained in the 71M653X Software User’s Guide (SUG). 1.4.6 UARTs The 71M6533 and 71M6534 include a UART (UART0) that can be programmed to communicate with a variety of AMR modules and other external devices. A second UART (UART1) is connected to the optical port, as described in the 1.5.6 Optical Interface section. The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as follows: • UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. • UART0 TX: This pin is used to output the serial data. The bytes are output LSB first. The 71M6533 and 71M6534 have several UART-related registers for the control and buffering of serial data. A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0 and S1BUF, SFR 0x9C for UART1). When written by the MPU, SxBUF acts as the transmit buffer, and when read by the MPU, it acts as the receive buffer. Writing data to the transmit buffer starts the transmission by the associated UART. Received data are available by reading from the receive buffer. Both UARTs can simultaneously transmit and receive data. |
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