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71M6534 Datasheet(PDF) 21 Page - Maxim Integrated Products

Part No. 71M6534
Description  Exceeds IEC 62053/ANSI C12.20 Standards
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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71M6534 Datasheet(HTML) 21 Page - Maxim Integrated Products

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FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
Rev 2
21
The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers
are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected
DPTR for any activity.
The second data pointer may not be supported by certain compilers.
DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions
faster compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save
and restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency.
By selecting the Evatronics R80515 core in the Keil compiler project settings and by using the compiler
directive “MODC2”, dual data pointers are enabled in certain library routines.
An alternative data pointer is available in the form of the PDATA register (SFR 0xBF, sometimes referred
to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction
MOVX A,@Ri or MOVX @Ri,A.
Internal Data Memory Map and Access
The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory
address is always 1 byte wide. Table 8 shows the internal data memory map.
The Special Function Registers (SFR) occupy the upper 128 bytes. The SFR area of internal data memory
is available only by direct addressing. Indirect addressing of this area accesses the upper 128 bytes of
Internal RAM. The lower 128 bytes contain working registers and bit addressable memory. The lower 32
bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select
which bank is in use. The next 16 bytes form a block of bit addressable memory space at addresses
0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing.
Table 8: Internal Data Memory Map
Address Range
Direct Addressing
Indirect Addressing
0x80
0xFF
Special Function Registers (SFRs)
RAM
0x30
0x7F
Byte addressable area
0x20
0x2F
Bit addressable area
0x00
0x1F
Register banks R0…R7
1.4.2 Special Function Registers (SFRs)
A map of the Special Function Registers is shown in Table 9.
Only a few addresses in the SFR memory space are occupied, the others are not implemented. A read
access to unimplemented addresses will return undefined data, while a write access will have no effect.
SFRs specific to the 71M6533/71M6534 are shown in
bold print on a gray field. The registers at 0x80,
0x88, 0x90, etc., are bit addressable, all others are byte addressable. See the restrictions for the INTBITS
register in Table 14.
Table 9: Special Function Register Map
Hex/
Bin
Bit
Addressable
Byte Addressable
Bin/
Hex
X000
X001
X010
X011
X100
X101
X110
X111
F8
INTBITS
FF
F0
B
F7
E8
IFLAGS
EF
E0
A
E7


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