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71M6534 Datasheet(PDF) 11 Page - Maxim Integrated Products |
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71M6534 Datasheet(HTML) 11 Page - Maxim Integrated Products |
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11 / 132 page  FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Rev 2 11 Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV[3:0] = 7) Time Slot Regular Slot Alternate Slot Register Typical Selections Register Typical Selections Signal Number Signal for ADC Signal Number Signal for ADC 0 SLOT0_SEL[3:0] 0 IA SLOT0_ALTSEL[3:0] A TEMP 1 SLOT1_SEL[3:0] 1 VA SLOT1_ALTSEL[3:0] 1 VA 2 SLOT2_SEL[3:0] 2 IB SLOT2_ALTSEL[3:0] B VBAT 3 SLOT3_SEL[3:0] 3 VB SLOT3_ALTSEL[3:0] 3 VB 4 SLOT4_SEL[3:0] 4 IC SLOT4_ALTSEL[3:0] 4 IC 5 SLOT5_SEL[3:0] 5 VC SLOT5_ALTSEL[3:0] 5 VC 6 SLOT6_SEL[3:0] 6 ID SLOT6_ALTSEL[3:0] 6 ID SLOT7_SEL[3:0] – – SLOT7_ALTSEL[3:0] SLOT8_SEL[3:0] – – SLOT8_ALTSEL[3:0] SLOT9_SEL[3:0] – – SLOT9_ALTSEL[3:0] The duration of each multiplexer state depends on the number of ADC samples processed by the FIR, which is set by FIR_LEN[1:0]. Each multiplexer state will start on the rising edge of CK32. FIR conversions require 1, 2, or 3 CK32 cycles. The number of CK32 cycles is determined by FIR_LEN[1:0]. 1.2.3 A/D Converter (ADC) A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6533/71M6534. The resolution of the ADC is programmable using the I/O RAM bits M40MHZ and M26MHZ (see Table 2). The CE code must be tailored for use with the selected ADC resolution. Table 2: ADC Resolution Setting for [M40MHZ, M26MHZ] FIR_LEN[1:0] FIR CE Cycles Resolution [00], [10] or [11] 0 1 2 138 288 384 18 bits 21 bits 22 bits [01] 0 1 2 186 384 588 19 bits 22 bits 24 bits Initiation of each ADC conversion is controlled by MUX_CTRL as described in Section 1.1.1. At the end of each ADC conversion, the FIR filter output data is stored into the CE RAM location determined by the MUX selection. 1.2.4 FIR Filter The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output data is stored into the fixed CE RAM location determined by the multiplexer selection as shown in Table 3. FIR data is stored LSB justified, but shifted left by eight bits. |
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