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71M6534 Datasheet(PDF) 98 Page - Maxim Integrated Products

Part No. 71M6534
Description  Exceeds IEC 62053/ANSI C12.20 Standards
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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71M6534 Datasheet(HTML) 98 Page - Maxim Integrated Products

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71M6533/G/H and 71M6534/H Data Sheet
FDS_6533_6534_004
98
Rev 2
5.3.7 CE Status and Control
CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful
for generating early power fail warnings, e.g. to initiate necessary data storage. It contains sag warning
flags for phase A, B, and C, as well as F0, the derived clock operating at the fundamental input frequency.
CESTATUS represents the status flags for the preceding CE code pass (CE_BUSY interrupt). Sag alarms
are not remembered from one code pass to the next. The CE Status word is refreshed at every
CE_BUSY interrupt. The significance of the bits in CESTATUS is shown in Table 57.
CE Address
Name
Description
0x80
CESTATUS
See description of CESTATUS bits in Table 57.
Since the CE_BUSY interrupt typically occurs at 2520.6 Hz, it is desirable to minimize the computation
required in the interrupt handler of the MPU. Rather than reading the CE status word at every CE_BUSY
interrupt and interpret the sag bits, it is recommended that the MPU activate the YPULSE output to generate
interrupts when a sag occurs (see the description of the CECONFIG register)
Table 57: CESTATUS (CE RAM 0x80) Bit Definitions
CESTATUS [bit]
Name
Description
31:29
Not Used
These unused bits will always be zero.
28
F0
F0 is a square wave at the exact fundamental frequency for the phase
selected with the FREQSELn bits in CECONFIG.
27
SAG_C
Normally zero. Becomes one when |VC| remains below SAG_THR for
SAG_CNT samples. Will not return to zero until |VC| rises above SAG_THR.
26
SAG_B
Normally zero. Becomes one when VB remains below SAG_THR for
SAG_CNT samples. Will not return to zero until VB rises above SAG_THR.
25
SAG_A
Normally zero. Becomes one when VA remains below SAG_THR for
SAG_CNT samples. Will not return to zero until VA rises above SAG_THR.
24:0
Not Used
These unused bits will always be zero.
The CE is initialized by the MPU using CECONFIG. This register contains in packed form SAG_CNT,
FREQSEL0, FREQSEL1, EXT_PULSE, I0_SHUNT, I1_SHUNT, PULSE_SLOW, and PULSE_FAST. The
CECONFIG bit definitions are given in Table 58.
CE
Address
Name
Data
Description
0x20
CECONFIG
0x5020
See description of the CECONFIG bits in Table 58.
The SAG_MASKn bits enable sag detection for the respective phase when set to 1. When SAG_INT is set
to 1, a sag event will generate a transition on the YPULSE output.
IA_SHUNT, IB_SHUNT and IC_SHUNT can configure their respective current inputs to accept shunt resistor
sensors. In this case the CE provides an additional gain of 8 to the selected current input. WRATE may
need to be adjusted based on the values Ix_SHUNT.
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by
the MPU if EXT_PULSE = 1. In this case, the MPU controls the pulse rate by placing values into APULSEW
and APULSER. By setting EXT_PULSE = 0, the CE controls the pulse rate based on WSUM_X and VARSUM_X.


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